In the workshop, user and vendor panelists spoke of such challenges as ensuring "correlation and convergence" of EDA tools, "clustering" analysis tools so they can work across different domains, and ensuring that silicon intellectual property (IP) data is represented in consistent ways. Speakers discussed design integration issues in electronic system level (ESL) design, design for manufacturing (DFM), and system-in-package (SiP) design, in addition to IC implementation.

John Darringer, manager for system-level design at IBM's T.J. Watson research center, introduced the workshop by noting that "tremendous progress" has been made in tool integration in recent years. Design systems have gone from slow file I/O interfaces to the ability to run applications in shared memory, he noted. But there are still a lot of "tin cans" connecting external and internal applications, Darringer said, and there's far more work to be done.

In the first of two panels, participants talked about today's challenges and solutions. Thomas Harms, director of alliance management at Infineon, noted that an integrated design system would ideally encompass system-level design, chip/package codesign, analog/mixed-signal design, IP reuse, functional verification, RTL-to-GDSII implementation, and test. But CAD departments today are forced to do a great deal of their own integration, he said.

"Interoperability through OpenAccess is only half the story," Harms said. "The other half is getting correlation and convergence between tools from different vendors." Other problems, he noted, include multiple tools with different algorithms, the requirements of working with competing vendors, and the need for accurate models to reflect silicon performance.

Harms predicted that design systems will be partitioned into "integrated subflows" from single vendors, with some third-party tools. "We believe there's a great opportunity for revolutionary business and partnership models," he said.

Philippe Magarshack, group vice president for central R&D and STMicroelectronics, said the next big integration challenge has to do with DFM. At issue, he said, are which formats and which data needs to be passed back and forth between the fab environment and the IC design tools. Magarshack said that a DFM "unified format" should allow lithography, critical area analysis, chemical metal polishing (CMP), and other effects to be addressed before fabrication. But it should be open rather than proprietary, he said.

The fundamental goal of a design system, said Rahul Goyal, director of EDA business at Intel, is to ensure predictable results. "To do things predictably, we need to get into more open platforms," he said. Specifically, said Goyal, the handoff between different domains — RTL design, implementation, and the DFM "back end" — needs better integration. And the OpenAccess database, he said, needs engines, applications and plug-ins to allow applications to be built on top of it.

Format incompatibility and data management are business problems rather than technical problems, said Antun Domic, general manager at Synopsys. Predictability, he said, is a much more serious technical problem — but one that's improving dramatically.

George Janac, president and founder of Silicon Navigator, agreed that good design is all about predictability. But with a disaggregated supply chain, he said, IP vendors wield a lot of control over design flows. What's key is not so much the format in which IP data is delivered, he said, as what's being done to organize the data.

"IC CAD really needs to look a lot more like FPGA CAD, and why FPGA tools are so much easier to use is that the data is organized," Janac said. He also said OpenAccess needs to be extended and "personalized" to deal with additional data formats.