"Each vendor supports a different subset of System Verilog features, and it is very hard for us to track who supports what features for what functions," said Thomas Thatcher, a staff verification engineer at Sun Microsystems Inc.

Sun has been using System Verilog assertions in verification since November 2005, but also uses more traditional approaches in simulation and does not yet use the language for test benches or design, he said.

"We need consistent support from all vendors in the industry, at least for a subset of synthesis and simulation features," said Akilesh Parameswar, a senior hardware engineer with Tensilica "Today some features are supported in simulation but not synthesis and vice versa," he added.

Tensilica is using System Verilog "extensively" for verification and is "highly likely" to use the language for its next major project for other features as well, he said. He noted some synthesis functions require encapsulation of System Verilog and have outputs that regress to Verilog-95.

Getting System Verilog support for both intellectual property blocks and EDA tools "is a chicken-and-egg problem," said John Goodenough, director of design technology at ARM.

The IP provider uses System Verilog "across the enterprise" for assertions and coverage. But so far it has only conducted pilot projects and some experiments for System Verilog with tech benches and in design. "The big benefit at the end of the day is convergence on a single design language," Goodenough said.

A Cisco Systems designer said it recently used System Verilog and System C as part of a design of a 3.2 million-gate security chip.

"This was a pilot project. Now we have three or four more projects following the same method we pioneered and using some of the libraries we developed," said Benjamin Chen, an ASIC verification engineer at Cisco.

In an example of how much fresh effort System Verilog required, Chen noted that EDA vendor Synopsys dedicated some of its best verification engineers to work in Cisco offices full time through all the design phases of the project. He expressed hope that future projects might require only occasional calls to Synopsys engineers. "I don't see designers at Texas Instruments accepting System Verilog because they see it as a verification language," said Somdipta Roy, a verification engineer in TI's wireless group. TI is using System Verilog for assertions and coverage in two or three projects now and will use it for some of its IP blocks as they go through a next-generation update, he added.

Transmeta, a designer of an x86-compatible processor, used System Verilog for verification and test benches in a new ground-up project started about a year ago. However it did not use any of the design constructs of the language.

"What's lacking from the EDA vendors is guidelines for when to use constraints in a good judicious way," said Shankar Govindaraju, a principal engineer at Transmeta. The company saw simulations speed up by a factor of ten while test time was reduced nearly in half, in part through use of System Verilog, he added.