Participating in a panel discussion on IC thermal issues here at the Design Automation Conference Tuesday (July 25), Pitts acknowledged that he is concerned about thermal impact at the "mid-45- and 32-nm" nodes, but that it is currently "not our No. 1 problem." Right now, "thermal is a second-order priority," Pitts said. Dynamic IR drop, he said, is chief among more immediate concerns.

But thermal gradient does remain a long-term concern. "Several trends are going in the wrong direction," Pitts said. "They have been going in the wrong direction for several technology nodes."

Among these trends are increasing chip power density and feature integration, Pitts said, as well as packaging options that further increase power density, such as stacked die and system-in-package modules.

Focus on thermal issues in IC design may be ahead of its time, according to Andrew Yang, Apache Design Solutions Inc. chairman and CEO, but it's important for EDA vendors to get the ball rolling now. Yang said EDA has historically tackled a problem in three stages: analyze, avoid, then fix. EDA needs to start analyzing this problem now, he said.

Yang's company rolled out an integrated electro-thermal tool for analyzing system-on-chip temperature's impact on leakage, timing, reliability and voltage drop last week.

"Are we creating a solution for a problem that doesn't yet exist?" Yang asked. "We have to be ready. We have to be two years ahead of the curve. We need to think about this now."

Three years from now, the semiconductor industry will be talking about fixing the thermal problem, according to Yang, who added that "it is a big problem."

Pitts said that TI, in the short term, can apply a methodology it has developed to leverage models across libraries to calculate thermal effects, such as temperature, voltage and leakage.

"We have some time, and we probably have some measures we can take [to push out the need for thermal analysis EDA tools]," Pitts said. But, he acknowledged, "We are getting to the point that we are going to get a lot of help from the EDA folks. We aren't there yet, but it's just around the corner."

A recent EE Times EDA Users Survey found that, as feature sizes shrink, designers expect that managing leakage current will become their biggest concern.