Xpedion (Milpitas, Calif.) is a provider RF design tools that last year forged a partnership with Gennady Gildenblat, co-developer of the public domain PSP model, to provide PSP parameter extraction for Xpedion modeling services.

In April, Xpedion claimed an industry first when it introduced a transistor-level phase-locked loop (PLL) solution for verifying complete closed loop noise and jitter, a breakthrough that the company said allows PLL designers to fully verify their designs prior to silicon to save design spins and reduce time to production.

"Increasingly, designers are finding that their high-performance RFIC designs are under-characterized," said Jim McGillivary, vice president and general manager of Agilent's EEsof EDA division. "The result is too many foundry turns and poor yield. Agilent is recognized as the leader in RF design and simulation, with proven breadth and depth. By adding Xpedion's products to our portfolio, we will be able to increase our emphasis on design verification and DFM [design-for-manufacturability], giving our customers an indispensable design flow covering RFIC design, design verification and DFM."

Pete Rodriguez, Xpedion's CEO, added, "Xpedion's and Agilent EEsof's combined technologies are used by almost all key companies designing RFICs."