Participating in panel discussion on building a verification test plan as part of the Design Automation Conference (DAC) here Thursday (July 27), Foster described the process of creating a verification plan as invaluable.

"The process of creating a verification plan allows us to truly understand the problem," Foster said.

The concept of push-button, automated design verification is not plausible, Foster indicated, because the process will always require a skilled verification engineer to put in the time and effort to decide, among other things, which blocks are good candidates for formal verification and which should be verified using simulation.

The process of verification is analogous to throwing a party, according to Ramin Hojati, founder and president of privately held EDA startup Averant Inc. Before the party, someone has to go in and decide what elements are needed as far as food, entertainment, etc., he said.

Prior to verification, "Somebody in a management position has to go in and figure out what is the chip intended to do and what needs to be tested," as well as what elements should be subjected to formal verification and which should be tested using simulation, according to Hojati, who was not included in Thursday's panel discussion.

"The mistake I see is that people jump right into writing assertions without stopping to think about what it is they are trying to verify," Foster said.

Foster noted that there "seems to be an ongoing battle between simulation and formal verification," but that a "modern-day verification renaissance man" understands that both have inherent strengths and weaknesses and puts the thought in to select the optimal solution for a given problem and set of constraints.