GRENOBLE, France — Temento Systems SA, a startup company with origins in a European supercomputer project, has developed a system-to-ASIC design and test software framework called Diatem that will demonstrated at Booth 94 the Design Automation Conference.

The company expects to bridge the gap between the design, manufacturing and maintenance teams which often have independent test strategies. This often wastes time and effort because the groups do not reuse the testbenches and test vector sets that have already been generated by others, Temento said.

Three major French organizations — Matra-BAe, an Anglo-French aerospace joint-venture; France Telecom; and the Commissariat a l'Energie Atomique (CEA) — are beta testing Diatem, which will become generally available in the third quarter of this year.

While the term framework may be out of fashion in the EDA industry these days, it describes Temento's software, which combines project and database management with hardware description language editing, testability insertion and test bench generation.

Diatem's top-down view of the test-management process is intended to provide a universal hierarchy of design, test and debugging that encompasses complete systems and boards down through multichip modules (MCMs), ASICs and individual cores. Temento expects that Diatem can be used throughout the life cycle of a product, including for remote test and maintenance, repair and field service operations.

Temento — the name is a condensation of "test and maintenance engineering tools" — was formed in 1995 from the French Advanced Computer Research Institute (ACRI) supercomputer project, where the team provided test solutions. Though the ACRI project was ultimately closed, Patrice Deroux-Dauphin and Christian Francois, Temento's cofounders and now its chief executive officer and vice president of engineering respectively, both said their work on the project taught them a lot about the testing of complex systems.

"Test for multiple boards is not available, and complexity problems are increasing with the introduction of things like ball-grid array packages, which mean you can't get bed-of-nails testers to access devices," said Deroux-Dauphin. "In the next five years system manufacturers will need these tools. Larger manufacturers will need them sooner."

Diatem provides an editing environment into which VHDL or Verilog can be written or imported. It also provides a management hierarchy to represent the design. "Designers should and can define boards in VHDL," said Francois. Once the design is present in an HDL format, a variety of styles of scan test chains can be automatically inserted into designs at the ASIC, MCM, pc-board or system level, to provide serial test access. From that point a test bench can be automatically generated for a software simulator, a hardware emulator or for physical prototypes.

Francois said Diatem supports Mentor Graphics' QuickHDL, Model Technology's V-sim and Cadence Design Systems' Leapfrog simulators. The software does not include test vector generation, but is able to work with third-party tools for this function. It includes debugging and analysis tools to display errors and test results.

One of the main claims Temento makes for Diatem is its ability to reuse test vectors and enhance them at each design or manufacturing step. The proper use of this feature can save 30 percent of the time and development cost of prototype testing and maintenance operations, the company said. The software is available for Unix or Windows NT platforms and is expected to have a price tag around $50,000 to $80,000.