SAN FRANCISCO — ARM Ltd., a pioneer of the IP core market as a licensor of 32-bit RISC microprocessor cores, has developed a synthesizable version of its ARM7 core.

The offering could spread the influence of ARM, as it departs from the company's traditional position of licensing 'hard' implementations of its architecture optimized for semiconductor licensors. With the introduction of a register-transfer-level synthesizable version, and given the architecture's simplicity and relatively limited transistor requirements, ARM cores could soon be used within programmable-logic devices and field programmable gate arrays.

However, Alistair Greenhill, ARM EDA tools manager, emphasized that for the moment the introduction of the soft core was an alternative delivery mechanism intended to supply ARM's existing semiconductor licensees and did not imply an immediate intention to broaden ARM's licensing policy.

Speaking at the Design Automation Conference, Tim O'Donnell, president of ARM's U.S. subsidiary ARM Inc. (San Jose, Calif.), said that the core had been re-engineered in conjunction with Synopsys Inc.'s Design Reuse group. The core was designed using guidelines set down in the Reuse Methodology Manual (RMM), a text authoured by Mike Keating of Synopsys and Pierre Bricaud of Mentor Graphics, O'Donnell said.

"The core is fully synthesable and was developed in line with the RMM and in conjunction with Synopsys. It can be optimized by each customer for speed, power consumption or size," said O'Donnell.

The ARM7TDMI-S soft core supports both the 32-bit version of the core and the Thumb variant, which allows instructions to be stored in a 16-bit format and expanded to 32-bits on-the-fly. It includes a single reference clock, synchronous design and a unidirectional bus interface. It is offered in Verilog or VHDL versions along with synthesis scripts, and supports automatic test pattern generation.

ARM claims the ARM7TDMI-S core offers increased flexibility in design, test and process portability while maintaining the same support that is available for the hard macro version, thus allowing system designers to make use of previously developed software and development tools, operating systems and application code.

"The development of this soft core alternative was the direct result of customer requests for a different way to deliver the features found in the industry-standard ARM7TDMI core," said Reynette Au, ARM's vice president of marketing. "Our customers wanted a core that was fully synthesizable with industry leading design tools, and compatible with standard ASIC design flows."

O'Donnell admitted that ARM cores derived from the soft version would usually occupy more space than an optimized 'hard' version, or could provide lower performance, but he declined to quantify the differences. "It's probably going to be bigger than a hard macro," he said.

While one way to increase process portability may be through the use of Synopsys' cell-based array (CBA) technology, which provides a set of physical libraries optimized for synthesis and ported to a number of foundry technologies, O'Donnell said ARM "doesn't see all the products going into CBA. The first example [of use of the soft core] is not CBA."

Craig Lyttle, director of the IP business unit of programmable-logic vendor Altera Corp., said his company is "certainly working with ARM. An ARM7 would take up more than 50 percent of one our largest devices today, and that makes it marginal right now. You usually want any major core to be less than 50 percent, leaving room to do other things. But with our next-generation technology, the ARM core would be down around 20 percent."

O'Donnell said a number of ARM's established semiconductor licensees had already added the soft core to their range.

The cost of the new ARM soft core was not discussed. It is expected to be significantly less expensive than the hard ARM cores, which are believed to attract initial payments of about $1 million, plus on-going chip royalties based on a small percentage of the final chip price.