SAN JOSE, Calif. — Armed with new technology that promises to make behavioral synthesis more practical and predictable, startup Meropa Inc. is preparing to release what it regards as ground-breaking software. The company believes it has achieved sufficient breakthroughs to challenge synthesis giant Synopsys Inc. in the marketplace.

Still in its infancy, behavioral synthesis takes in high-level HDL descriptions, performs scheduling and multicycle resource allocation, and outputs code that can be synthesized to gates using conventional synthesis tools. Synopsys' Behavioral Compiler represents a largely automatic approach, while other providers, such as Cadence Design Systems, have emphasized an interactive methodology.

Compared to competitive tools, Meropa claims its flexible architectural-synthesis technology (Fast) offers a more flexible and intuitive coding style; can synthesize all parts of a design, including very dense state machines; and offers more predictability through technology-specific timing optimization. The company claims to support a number of design domains, including networking, wireless telecom, DSP, multimedia, and controllers.

"The big problem with behavioral synthesis to date has been the lack of predictability," said David Knapp, Meropa president. "There's been a large discrepancy between what you get at the gate level and what's been predicted. We've solved that problem."

"We honestly believe this technology is going to change the way design is done," said Pradeep Fernandes, Meropa director of marketing.

Meropa faces the same challenges as other EDA startups — to establish credibility, to compete against the vast marketing resources of big vendors, and to sign up ASIC vendor support, which is required for Meropa's technology.

But the company's bold claims are backed by experience. Knapp, a former professor at the University of Illinois, has been researching high-level synthesis since 1981, and he participated in the development of Synopsys Behavioral Compiler. Fernandes and Marco Rubinstein, applications director, have also worked at Synopsis.

Meropa's first challenge is to get designers to embrace the new methodology behind behavioral synthesis. The company claims that a high-level synthesis methodology lets users write 80 percent less code, debug designs faster, predict timing behavior earlier, and still switch to different processes or architectures with relative ease.

The next challenge is "why Meropa" as opposed to one of the more established providers. For one thing, Meropa claims to have fewer coding-style restrictions than other vendors, and to support a more "flexible" Verilog subset that permits a wider range of descriptions.

"The syntax is the same, but the class of machines you can describe is much larger," said Knapp. "Competing products can't synthesize all of the state machines we can synthesize. If you have a very dense state graph with a lot of branches, the others will add extra states."

Another advantage claimed by Meropa is predictability. The company will require the use of technology-specific libraries, and behavioral synthesis is run in concert with static-timing analysis, which optimizes the finite state machine, control logic, multiplexing and datapath components.

Rubinstein acknowledged that Meropa is "just getting started" in its discussions with ASIC vendors, but he said the company has developed an easy way of generating library support "in a matter of minutes." Fernandes said the company is talking to Aspec and LSI Logic, among others.

Meropa's Fast technology lets users create multiple architectures for a single source description. It supports loop pipelining based on designer specifications of throughput and latency. It also provides datapath component generators for adders, multipliers, ALUs and other elements, thus claiming a capability similar to Synopsys' DesignWare library.

Like Synopsys' Behavioral Compiler, Meropa is offering a highly automated behavioral-synthesis product. But it also permits a high degree of interactive control through scripts, as well as a graphical user interface.

To use Meropa's Fast technology, designers create behavioral Verilog descriptions and provide constraints such as technology library, clock period, and throughput and latency goals. Designers can also issue directives to map arrays onto RAMs, bind operations to resources, and pipeline loops.

The product outputs modified-behavioral Verilog with new state information, synthesizable-RTL Verilog, and gate-level net-lists. Although the product can go all the way to gates, and does so for the sake of predictability, it doesn't accept RTL input and is not intended to compete with Synopsys' Design Compiler.

Meropa is doing its development work under Linux and will first offer the product on Sun Solaris platforms. The company is in beta sites now and expects to formally announce and ship the product by September of this year.