SAN FRANCISCO — Mentor Graphics Corp. (Wilsonville, Ore.) is bringing its silicon intellectual property portfolio closer to silicon with the announcement of three major contracts with large semiconductor companies at this week's Design Automation Conference. A contract with Motorola Inc. is said to be the biggest consulting deal in Mentor's history, eclipsing a previous $17 million deal.

Motorola will develop an enterprise-wide IP integration methodology with Mentor as a partner, while IBM will make the MentorIP virtual library cores part of its Blue Logic family of cores, which were recentely announced as part of an expansion of IBM's ASIC offerings. And United Microelectronics Corp. has become a Premium Silicon Partner for MentorIP, using process technologies currently in production as well as a 0.18-micron process to be available next year.

"Our goal is to offer customers truly reusable IP, while avoiding the system-integration headaches," said Bernd U. Braune, senior vice president responsible for Mentor's Microtec software, IP and Meta emulation divisions.

"To that end, our library of verified cores has been specifically designed for reusability and for IP-based integration methodologies that can be implemented in customers' flows."

Motorola's multi-year program calls for the reusable cores to be turned into products to Motorola's specifications, "making Mentor's IP consulting services essential for developing this program," according to Arturo Krueger, corporate vice president and general manager of Motorola's Advanced Technology Lab.

Open Library support
Meanwhile, Mentor also announced enhancements to its IP services business, including a readiness to support OLA, the ASIC Council specification for an Open Library API. To that end, Mentor demonstrated its static timing analysis and design-for-test tools at the Design Automation Conference here last week. The products were running off a select body of ASIC Council members' libraries, including those from IBM, LSI Logic, Motorola, NEC, Texas Instruments and VLSI Technology.

Mentor has also added features to Renoir '98, its graphical design environment, to reflect interactivity with IP cores, better design browsing and an enhanced HDL-to-graphics interface for state machines and flow charts. With HDL2Graphics, designers can automatically read in VHDL, Verilog or mixed-HDL text code and create graphical designs.

The company has also announced a multiyear partnership with Ambit Design Systems to incorporate Ambit's BuildGates into Mentor's IP design flow. BuildGates purportedly reduces the time users spend in the synthesis phase of design and also offers capacity improvements over current synthesis methods. Under the agreement, Mentor's IP division and consulting teams will use BuildGates for deep-submicron systems-on-chip.