SANTA CLARA, Calif. — Stepping into the forefront of an emerging methodology shift, Chip Express will announce a register-transfer level (RTL) sign-off service at next week's Design Automation Conference. The service will allow selected customers to work at a higher level of abstraction and avoid implementation details.

Though most ASIC sign-off today takes place at the gate level, that methodology is changing due to the need to tightly couple synthesis with physical design for very deep-submicron geometries. As a consequence, some designers are starting to do their own physical design, or are opting for RTL sign-off and letting the ASIC vendor handle both synthesis and layout.

Chip Express offers a one-day gate array prototyping service, coupled with one-week and one-month production options. Depending on design complexity, it can take a user's RTL code and have a silicon prototype within two weeks, said Jonathan Park, manager of the Chip Express design center.

"Our products are aimed at time-to-market solutions," said Park. "We are trying to expedite not only the prototyping stage, but also the design implementation stage." Many designers, he noted, are not experts with synthesis and face a steep learning curve before they can get to gate-level sign-off.

While RTL sign-off is not likely to appeal to designers who are trying to squeeze every nanosecond out of silicon, it's not just for slow designs, Park said. He said Chip Express has used it on a 100-MHz chip.

The RTL sign-off program is aimed at customers going to production with Chip Express silicon, and they will be carefully screened, Park said. "This is a very engineering-intensive service. We could expend a lot of work for people interested in only doing emulation, and our resources are not that big." Chip Express will evaluate RTL code and timing specification to ensure the design is "clean," synthesizable and can meet performance goals, he said.

To use the service, customers provide RTL code in VHDL or Verilog, a system timing specification, I/O pad specifications, package pinouts and a test bench. Chip Express uses code-coverage tools to evaluate the code, and then performs synthesis using Synopsys tools.

The output at this stage is a gate-level net-list ready for layout with static timing, testability test coverage and layout power reports. Scan insertion and automatic test-pattern generation are provided by customer request. The output is sent to the designer for verification and approval.

The final stage is layout and back-annotation verification. A post-layout static timing report is submitted to the customer. Then the design goes to silicon. RTL sign-off is available for Chip Express' entire line, including its recently announced 0.35-micron gate-array family.

Since the process is service-intensive, there is no set price for RTL sign-off, Park said. He noted that RTL sign-off has already been performed with roughly 10 customer designs.