SAN FRANCISCO — Promising to automate some of the most challenging aspects of custom chip design, startup Sycon Design Inc. is announcing its first products at the Design Automation Conference. The company said it is a unique approach with technology that performs routing before placement.

Sycon will unveil Tempest-Cell, an automatic cell-layout synthesis tool, and Tempest-Block, a hierarchical block assembly tool. The latter offering includes RoPRo, a tool that implements Sycon's "route-place-route" methodology.

"We are offering handcrafted-quality performance, density and speed in a fraction of the time it takes today," said Brani Buric, vice president of marketing for Sycon Design Inc. (Saratoga, Calif.). The company's goal, he said, is to automate custom design processes that are done manually now.

Tempest-Cell takes in a flat or hierarchical Spice net-list, silicon process technology information, a user-defined global architecture and user-defined local constraints. It produces a cell layout in CIF and LEF formats.

The tool will automatically place transistors, and split transistors to fit into the predefined cell architecture. Users can define special transistor groupings, fixed transistor locations and transistor-to-transistor relationships. Tempest-Cell employs a shape-based router.

Buric said Tempest-Cell is aimed at library developers and structured custom designers. He said it can design cells with as many as 400 or 500 transistors, and offers "beyond traditional 100 percent utilization." A future release, he promised, will handle dynamic logic.

"This is not symbolic layout and compaction, but place and route with minimum design rules," Buric said. "The tool has much more flexibility in what it can accomplish and is extremely fast. It can generate most cells in a fraction of a minute."

Tempest-Block is aimed at blocks with as many as 100,000 transistors, and can handle high-performance designs of 300 MHz or more. It takes in a structural Verilog net-list and the cell-design library in formats such as CIF and LEF. It outputs finished block layouts in CIF or LEF.

Users define a variety of block constraints, such as block-level pin location, metal widths and spacing per net, power strapping, clock-net distribution pre-routing, signal shielding, cross-coupling, routing blockages and skew. Tempest-Block analyzes the net-list for structures such as buses, bit ordering and control signals.

This information is then forwarded to RoPro, which includes a shape-based router and a placement algorithm. An initial routing and placement are followed by a routing touch-up. "Unlike traditional methodologies, we minimize the influence of parasitics by routing first, and then placing the cells underneath," said Buric.

The router can understand the repetitive and multibit characteristics of data signals. It claims to generate straight routes with branches closest to estimated port locations. Data-bus routing is skew sensitive, while all other routing is wire-length sensitive.

The router accepts physical constraints such as block size and pin positions. A later release will directly tackle electrical timing and power constraints, Buric said.

Sycon will aim for project- or time-oriented licensing. But it is offering a perpetual, single-seat license for Tempest-Cell at $250,000, and for Tempest-Block at $200,000.