IRVINE, Calif. — Saying it will offer the first high-level synthesis environment specifically crafted for intellectual property (IP) reuse and integration, EDA startup Y Explorations Inc. will demonstrate its Explorations suite of tools at the Design Automation Conference in San Francisco later this month. The company is attempting to commercialize research at the University of California at Irvine led by professor Dan Gajski, a well-known synthesis researcher.

Y Explorations is actually the second attempt to commercialize Gajski's work. Several years ago, Gajski and several associates started Irvine Research to market behavioral synthesis tools. The company was reborn in 1995 as Y Explorations, with a new mission to provide high-level design tools that can accommodate predefined blocks.

Foreign objects
"We're offering high-level synthesis that knows how to deal with foreign objects," said Gajski, who serves on the Y Explorations board of directors. "For system-on-chip design, you have to encapsulate IP and put it into the design. I don't see other vendors doing that."

Y Explorations will offer a tool called Explorations Database (XD), which allows IP developers to "capture" reusable blocks and generate functional descriptions. The blocks then become black boxes that can be selected by the company's synthesis tools, Explorations Compiler (XC) and Explorations Environment (XE).

The tools are in beta sites now and are intended for shipment in the third quarter.

"EDA vendors today are looking at top-down design methodologies," said Viraphol Chaiyakul, Y Explorations' president and chief executive officer. "Our methodology is different. It's what we call 'meet in the middle.' We believe IP should be designed from the bottom up first. Our synthesis methodology uses predesigned blocks to create a bigger system."

Chaiyakul, like most other employees of the seven-person company, is a former student of Gajski's. He worked at UC Irvine as a research specialist and has 10 years' experience in high-level synthesis.

The company's tools are aimed both at IP creators and IP integrators. IP developers will use XD to capture functional specifications for hard or soft blocks. "You describe how to use a component to perform certain operations," Chaiyakul said. "If it's an MPEG core, you tell the database how the core will be used to perform MPEG functions."

As a result, he said, the IP integrator will be able to use the block in a "drag and drop" fashion, without having to know the internals of the block. This allows IP protection without encryption. Moreover, Y Explorations synthesis tools will be able to select the IP blocks and generate interface logic.

XC is an automatic synthesis tool that reads in behavioral VHDL, and outputs RTL (register transfer level) code in the Synopsys synthesis subset. A future release will support Verilog. The product provides the basic features of behavioral synthesis, including resource allocation and sharing, scheduling and architecture selection. Users control the synthesis process through area and performance constraints.

Small steps
What sets XC apart from other behavioral synthesis tools, Chaiyakul claimed, is its ability to read the functional IP descriptions created by XD. If the scheduler sees a function that can be satisfied by a given block, it pulls it into the design. It also generates a state machine to communicate with the IP blocks. XC's output is actually one controller block and a number of IP blocks; the user has only to synthesize the controller.

Another advantage claimed by Y Explorations rests in its other synthesis tool, XE. This tool is essentially a graphical, interactive version of XC that allows what Chaiyakul called "a lot of small synthesis steps." Users can interactively perform scheduling, resource allocation and other tasks for performance-critical portions of a design.

Chaiyakul said that XE will generally be used for 5 to 10 percent of a design, while the automatic XC will handle the rest. An "online algorithm" enables XC to complete a partial design, using the completed critical section as a constraint.

In addition to VHDL text, XE can accept several types of graphical input. These include block diagrams, state-machine bubble diagrams and a proprietary "cycle-based spreadsheet." Chaiyakul described the latter method as a "state action table" in which the user describes register transfers in a spreadsheet format.

The synthesis tools provide performance estimates, using an internal static timing analyzer. Timing constraints can be given at a behavioral, state, cycle or event level. Area constraints are specified in terms of component or bus resources.

A final product, Explorations Shell (XELL), provides a Tcl/Tk interface that allows tool customization and extension, and access to synthesis algorithms.

Y Explorations will show its products in a private demo suite at DAC. Pricing information is not yet available.