SAN FRANCISCO — EDA companies have to produce new tool solutions, improve tool interoperability and devise better Internet solutions for the coming era of nanometer design, according to panelists at the CEO Plenary Panel here at the 35th Design Automation Conference.

The panel, hosted by Thomas Pennino of Lucent Technologies, was comprised of three users and the chiefs of three EDA powerhouses. The users were Gadi Singer, general manager of design technology at Intel Corp.; Johan Daneels, president and chief executive of Alcatel Microelectronics; and Robert Brodersen, a professor at the University of California, Berkeley. On the EDA side, the panelists were Jack Harding, president and chief executive of Cadence Design Systems, Aart de Geus, chairman and chief executive of Synopsys Inc., and Wally Rhines, president and chief executive of Mentor Graphics Corp.

Chief on the minds of the users on the panel was how the EDA industry plans to help designers become more productive to deal with the increasing gate counts and clock rates of nanometer design.

"Within a year and a half to three years, we can expect to see designs ramping up to 0.18 micron, with speeds approaching 1 GHz," said Intel's Singer. "In the near future, we will have systems with 50 million to 100 million transistors — systems doing multiprocessors — and some of the validation techniques we are using are already 12 years old."

Singer believes the new era will require tools that better address noise problems and reliability and that offer picosecond accuracy. IC industry leaders "are going to continue to double their frequency and double design capacity; however, some of the current tools are going to run out of steam in the next five to six years," Singer said. "We need to see the next generation for nanometer design.

New tools needed
"The question is: Is the EDA industry really set to meet the nanometer design challenges?"

Mentor's Rhines said the industry is already creating new methodologies, but he acknowledged that EDA vendors must turn out static-timing, dynamic-timing, parasitic-extraction and verification tools to tackle high-frequency ranges.

The panelists further called for greater tool interoperability as a means for improving design productivity.

Alcatel's Daneels noted that new designs will be increasingly time-consuming and that to meet time-to-market goals, system houses will have to be able to determine hardware and software partitioning up-front. Tool interoperability will be critical to bringing the software and hardware worlds closer together, Daneels said.

"The process of hardware/software codesign would be helped quite a bit if EDA providers would cooperate [with one another]," said Daneels.

Cadence's Harding acknowledged that the EDA industry has had "a poor history of collaboration, cooperation and gentlemanly rapport" but said he believes that the industry is maturing. He cited Cadence's plan, announced at DAC, to license its Library Exchange Format (LEF) and Data Exchange Format (DEF) to all interested parties in 1999.

Not to be outdone, Synopsys' de Geus announced that Synopsys will license its timing constraints. "We have made available the RTL subset, PDIF, SWIFT, .lib and, now, timing constraints. That is all we got. Now I hope the pressure switches to others to further interoperability."

UC-Berkeley's Brodersen called for greater use of the Internet to deal with growing design complexity.

Software complexity and tool interoperability are stumbling blocks for educating engineers, Brodersen said. He proposed that EDA vendors provide virtual training services and run tools via the Internet, "instead of having us try to figure out how to get the software to work on our machines and take care of the updates."

A benefit of the Internet-centric approach, in Brodersen's view, would be that it would "make it possible for the EDA industry to have to deal with all the bugs."