SAN FRANCISCO — Hardware/software codesign tools that use the telecom arena's system-design language are being developed by Arexsys (Grenoble, France). The tools leverage leading French research into high-level architectural modeling and synthesis.

The Arexsys tools will include the ability to parse complex behavioral descriptions in a mix of system-design language (SDL ), VHDL and C and synthesize it to VHDL description of the hardware and a C file description of the software.

Arexsys received seed funding from the TIMA laboratory of the French National Center for Scientific Research in Grenoble and is using results from research there to develop high-level tools that can act as a system- and architecture- based front-end to standard EDA tools. SDL has been used for years to describe telecommunication systems and protocols.

Arexsys expects to have its products into beta sites this summer and to have production software ready by the end of 1998.

The company was founded by Ahmed Jerraya, research director at the TIMA Lab, who will act as chief scientific officer; Jean-Pierre Moreau, director of research partnerships at STMicroelectronics; and Francois Constant, formerly southern European regional manager for Synopsys.

Jerraya is a respected researcher in the field of systems-level design and next-generation design languages.

Arexsys is developing three tools: a simulation backplane for system description in multiple languages, an architecture exploration tool to allow hardware/software trade-offs to be explored and a hardware/software cogeneration tool that will synthesize VHDL and C and automatically generate interfaces between the hardware and software.

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