SAN FRANCISCO — Stating that it is aggressively attacking the challenges of design reuse, Mentor Graphics Corp. has unveiled a campaign to help customers better handle and integrate IP. The effort includes greater participation in open standards, an entry into a core alliance with IBM and the introduction of core-friendly versions of its Renoir ESDA tool and ModelSim simulator. The company announced its plans at the 35th Design Automation Conference (DAC).

"At last year's DAC . . . everybody talked about the issues but nobody offered solutions," said Bernd Braune, senior vice president at Mentor (Beaverton, Ore.). "So, this year, we are focusing on four areas and going beyond talking about reuse. We are promoting open standards so people can pick the best tools, providing cores to customers that are very robust, providing them with design services to help them develop an IP-driven design methodology, and giving them tools that are more IP-compliant."

On the standards front, Mentor said four of its tools support SI2's Open Library API (OLA), a commitment to create OLA libraries, and an OLA partnership with ASIC-synthesis vendor Ambit Design Systems. Mentor said it has added IBM to its core-alliance partnership.

On the services side, Mentor said it has signed a multiyear contract with Motorola to build a system-on-chip IP design flow.

Boom time?
Braune said creating reuse methodology is a booming business. "We feel it is a new industry. The feedback we get is that . . . to make design blocks reusable, people have to spend three times the budget they spend to create it," said Braune. Companies ask Mentor, he said, to source IP from the market, test it, validate it and integrate it into their design process.

With IC gate counts rising 10x every five years, Braune predicts, the reusable portion of IP will also increase at a rate of 10x. By 2003, the company predicts, silicon capacity will average 5 million gates: 500k from the previous design, 500k from created IP and the remaining 4 million from external design groups or third-party core providers.

"To prepare for a 5 million-gate design, companies have to begin now to create a design-for-reuse strategy," said Braune.

On the tool front, Mentor announced core-friendly versions of the Renoir ESDA tool and ModelSim simulator.

Kevin Curtis, general manager for Mentor Graphics' HDL Design Division, said the new Renoir '98 has better interactivity with IP cores, better design browsing and enhanced HDL to graphics for state machines and flow charts. The main feature is HDL2Graphics. Designers can automatically read in VHDL, Verilog or mixed-HDL text code and create graphical designs.

The company also will offer a new language-neutral-licensing (LNL) option with its ModelSim simulator. For a single license at $18, 755, customers can simulate in either Verilog or VHDL.

"With LNL, we have introduced a whole new concept to simulation," said John Ott, director of marketing and sales at Mentor simulation subsidiary Model Technology. The LNL option licenses at $29,000.