SAN JOSE, Calif. — A new approach to logic verification from a closely watched EDA startup will debut this week, as 0-In Design Automation Inc. announces first shipments of its 0-In Check tool to development partners. The product is claimed to be the first commercial "white-box" verification tool, or one that can derive logic checks by looking at a design's internal structure.

While today's verification tools are black-box products, which look at a design's outputs, 0-In argues that white-box tools will directly find bugs that are unlikely to appear in simulation runs. 0-In Check uses synthesis technology to generate "checkers" that look for specific problems when simulation is running.

0-In came into public view early last year, when it announced its mission to create a class of tools that would combine elements of synthesis, formal verification and simulation. Chairman and chief executive officer Curt Widdoes is an EDA pioneer who founded Valid Logic Systems and Logic Modeling Systems. Steven White, the startup's president, was vice president of design verification at Synopsys from 1994 to 1996.

The company is developing a second product, 0-In Search, that uses formal verification techniques to track down "corner case" bugs following simulation. That product is being used on production designs in-house but has not been shipped.

0-In Check so far has gone only to selected development partners, and no date has been set for a production release.

One such partner is Argon Networks Inc. (Littleton, Mass.), which is using 0-In Check to help verify a switch-and-router Internet chip that contains several million gates. Kurt Baty, an ASIC designer and consultant working at Argon, said the product has given visibility to problems that otherwise might have gone unnoticed.

The key to white-box verification, said Paul Estrada, vice president of verification engineering at 0-In, is an ability to look at the internals of the design — in this case, a flat, register-transfer-level Verilog net-list — and figure out the best way to check logic functionality. Estrada said 0-In Check is "orders of magnitude" more efficient than simulation alone for finding many types of bugs.

Originally developed to check for register leaks, 0-In Check now enables around 30 different kinds of checks and can find such problems as full-case and parallel-case violations in muxes, counter overflow and underflow and memories that are overwritten without being read. It can find unpropagated bugs that won't show up at a design's outputs during simulation.

"The problem with simulation is that low-probability events don't get exercised," said Estrada. "If you have a one-in-a-trillion-cycle bug, silicon will hit it once an hour. But simulation will take millions of hours, and you'll never simulate that long."

Widdoes likened 0-In Check to Purify, a program from Rational Software that is used by software developers worldwide to detect otherwise unobservable bugs. "Purify takes an existing program and looks for low-level bug signatures," he said. "We applied that concept to hardware and found there were such signatures for bugs that can be caught at a low level."

Third-party programs
0-In has already joined Cadence Design Systems' and Synopsys' third-party partnership programs, and it's working with both companies to ensure integration of its products with existing design methodologies, Estrada said. But 0-In plans to sell products on its own and does not have OEM relationships with those EDA vendors.

0-In Check and other white-box verification tools are designed to supplement, rather than replace, existing offerings. "Black-box tools are directly verifying the high-level behavior and only indirectly verifying corner cases," Estrada said. "We do the opposite. White-box tools directly verify corner cases and only indirectly verify high-level behavior."

That suggests that 0-In Check likely will be used for regression testing toward the end of a design cycle. But Estrada noted that some of the development partners are using it to check HDL code before simulation begins. Like today's "lint" tools, 0-In Check finds coding problems, but more significantly, it generates the checkers that find logic problems.

Inserting checkers into simulation runs to monitor internal signals or states isn't new. Leading-edge processor teams have done so for years, and a paper from the 1996 Design Automation Conference by Digital Equipment Corp. described the use of such checkers to verify the Alpha 21164. What's new is a commercial tool that can address various design environments.

0-In Check begins by synthesizing an internal, flat net-list for the entire design. It then identifies key elements, such as shared registers, memories, buses and counters. Next, it applies a set of predefined HDL design rules to synthesize the checkers. It can produce hundreds of checkers for every 100,000 gates of control logic in a design.

The tool's output is a test-bench-independent HDL file that can be added to any existing simulation. Reports following the simulation provide in-depth debugging information for each design-rule violation, along with waveforms.

So far, 0-In Check supports the Verilog-XL and Synopsys VCS simulators, with others to be added according to user demand.

The synthesis process is similar to the front end of commercial synthesis tools; what's not provided are the back-end optimization and technology mapping. That's because the only purpose is to create a large, flat net-list that allows 0-In Check to monitor potential problems across the entire design. Estrada said that 0-In Check has synthesized designs with up to 3 million gates and that it can compile a 100,000-gate design and create checkers in 5 minutes.

0-In Check creates four classes of checkers: static, basic, advanced and user. Static checkers detect net-list problems, such as function variables, that may retain their previous values. Basic checkers monitor muxes, buses, indexes and addresses for simulation-to-circuit mismatches. Advanced checkers ensure data integrity, watching for such problems as register leaks. User checkers let designers synthesize their own checkers.

While the checkers are nonintrusive with respect to the design, they do slow simulation. Estrada said that a simulation run with all checkers enabled could have around 70 percent overhead. But users can decide which checkers they want to run in any given simulation.

0-In Search, when available, will be a follow-on that uses the simulation as a starting point.

0-In hasn't yet determined the exact configuration or pricing under which its products will be offered. But the company will preview its technology at this month's Design Automation Conference.