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Posted: 3:00 p.m., EDT, 6/12/98
Mentor and Synopsys cooperate on "reuse" manual SAN FRANCISCO The consistent lag between the abilities of design tools and IC technology has led two EDA stalwarths to collaborate on a manual that describes a systematic strategy for design reuse. Mentor Graphics Corp. and Synopsys Inc. will launch their "Reuse Methodology Manual" (RMM), published by Kluwer Academic Publishers, at the Design Automation Conference. While the RMM contains no "silver bullet" solutions -- just overviews and common-sense guidelines its value may reside not only in its details but in its point-of-view. Just as "Introduction to VLSI Systems," by Carver Mead and Lynn Conway, became a seminal work for the design community some 20 years ago, and is now recognized as essential to understanding "top-down" design, Mentor and Synopsys hope the RMM becomes a bellwether for today's system-on-a-chip designers, and to have an effect similar to Mead and Conway's book, which was a stimulus for new tools such as silicon compilers, and helped prompt the industry to higher levels of design abstraction for VLSI chips.
The RMM may also be a potential seed for the "crystallization" of widely agreed upon design rules that could ease the exchange and integration of cores from multiple sources. InterHDL Inc. (Los Altos, Calif.), for one, will announce its support for RMM's rules in an agreement with Synopsys, wherein it will develop technology to automatically check that IP cores comply with RMM guidelines. Written by Michael Keating, director of engineering at Synopsys (Mountain View, Calif.), and Pierre Bricaud, director of the R&D center for the intellectual property division of Mentor Graphics (Beaverton, Ore.), the reuse manual means to describe how to design reusable hard and soft macros, and how to integrate them within a system-on-a-chip design within an appropriate design flow. Bricaud said Synopsys and Mentor were already discussing the possibility of refining and extending the text with input from a number of semiconductor manufacturers to create a broader industry reuse manual. Work along these lines would begin almost immediately, although the format and frequency of updates to the RMM has not been decided, Bricaud said. Most semiconductor makers have their own internal style guides on how to create cores. However, getting them to share or modify their internal practices for the sake of the larger industry is already proving to be difficult in forums such as the Virtual Socket Interface alliance. "Our hope is that the RMM will form a baseline for design for reuse," Keating said. "One of the biggest needs is for a consistent and effective design-reuse methodology. This includes coding and synthesis guidelines, as well as verification. Most importantly, it clarifies the deliverables for reusable IP and how to create them. The RMM is an important first step in addressing these needs." Bricaud added: "The hope is that IPs that will be created by the design community will be interchangeable with a minimum effort, therefore opening up the huge IP market, as predicted." The 240-page hardcover has grown out of a Design Reuse Partnership between Synopsys and Mentor, and was built on Synopsys' expertise in design tools and Mentor's experience in core creation. As a result, Synopsys and Mentor have stressed the objectivity of the text. "The RMM has been written to be as technically accurate and as tool-independent as possible," a Synopsys spokesman said. "It was very clear from the outset that the book would be poorly received if it was seen as merely a marketing vehicle for a specific tool suite. Considering the importance of synthesis for soft IP, the authors did get very specific in how to use the tools effectively. But the book frequently mentions third-party and competitive tools. Our hope is that any engineer working with any set of EDA tools can benefit from the book." InterHDL will support the RMM and its design-reuse goal by developing technologies that automate the qualification of commercial and proprietary IP cores. InterHDL anticipates beta testing of products derived from its partnership with Synopsys to begin in the fourth quarter of 1998. "One of the primary barriers to realizing the benefits of reusable IP is the unpredictable quality and style of the RTL code that it is written in," said Saeid Ghafouri, president and chief executive officer of InterHDL. The Reuse Methodology Manual will be available in bookstores and can be ordered online from Kluwer Academic Publishers.
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