LOS ALTOS, Calif. — Reshaping the company's mission and bringing new technology to market, InterHDL Inc. released four register-transfer level (RTL) planning and analysis tools at last week's Design Automation Conference. The tools include products that check for design errors, analyze testability, report code coverage and estimate power for RTL designs.

InterHDL is also offering new versions of the Verilint and VHDLlint products for which it is best known. But the company says the new tools are mostly first-of-their-kind offerings, and InterHDL believes they can have a strong impact on design productivity.

"We have enough of an arsenal to detect a significant number of problems at the register-transfer level," said Saeid Ghafouri, the new president and chief executive officer of InterHDL (Los Altos, Calif.). "It really does seem we can catch over half of the problems you'd find in simulation or synthesis, and catch them at the register-transfer level."

The first new offering, Checkit, is a hierarchical analysis product designed to uncover combinatorial and asynchronous loops in RTL modules. Checkit also identifies clock domains, which are portions of a digital circuit driven by a common clock. It notifies the user of all mixed-clock domains, which can also cause problems for analysis tools. Checkit includes a hierarchy browsing feature and offers forward and backward tracing.

"The real beauty of this product is that other tools require you to identify these things and eliminate them," said Kevin Jorgensen, InterHDL's vice president of marketing. He noted that Checkit provides a graphical user interface that lets users see the loops in the RTL code.

Testit is claimed to be the first product to provide RTL testability analysis. Designed in cooperation with Sunrise before its acquisition by Viewlogic, Testit performs more than 30 technology- independent testability checks. For example, the product checks for unobservable logic, unscannable flip-flops and uncontrollable clocks. It finds code that will cause such problems as timing violations, race conditions, glitches and loss of test coverage.

InterHDL can add more checks at the user's request, and a future release will provide an application programming interface so users can add their own, Jorgensen said.

Coverit is a code-coverage tool that has one significant difference from most such products: the ability to generate a "power profile" identifying possible power problems in a design. Coverit also claims to run much faster than competing products.

The power profile captures the switching activity of signals, variables, expressions and conditional branches. It identifies problems such as flip-flops with gated clocks.

For actual power estimation, users can turn to Coolit, an RTL and gate-level power analyzer competitive with the Watt Watcher product from Sente Inc. It's a static analysis tool, but it can use simulation vectors for added accuracy. Coolit uses what InterHDL calls "activity-driven" algorithms rather than a purely statistical approach.

Jorgensen said the product comes to within 20 to 30 percent of silicon at the register-transfer level, and to within 10 percent at the gate level. Taking a conservative approach, Coolit always overestimates power. It requires no additional ASIC vendor libraries, since InterHDL has extracted power information from existing libraries. The product checks for switching and short-circuit power, but not for leakage power.

In addition to the new products, InterHDL is releasing Verilint 5.0, which can handle larger designs and process up to 5,000 lines of RTL code per second. VHDLlint 2.0 includes a new graphical user interface and source navigator, and improved performance for large designs.

A new set of packages, called Prelude, offers various configurations of these tools. The four new products and VHDLlint 2.0 will be available in the third quarter, while Verilint 5.0 is available now. InterHDL products run on Unix and Windows NT workstations. Prices range from $20,000 for Verilint or VHDLlint to $55,000 for Coolit.