SAN FRANCISCO — Members of the Virtual Socket Interface (VSI) alliance announced new members and tipped a few details of their plans for rolling out additional guidelines and specifications this year to serve the many gaping holes that still lay along the route to developing a full-blown system-on-a-chip design methodology.

But at a Tuesday panel session at the Design Automation Conference here, those holes appeared significantly larger than the patches being prepared by various VSI working groups.

Intel Corp.'s embedded systems group, drive maker Seagate Technology and United Microelectronics Corp. were among nine new members who have joined VSI, bringing total membership to more than 180 companies. And additional technical results, beyond two sets of guidelines formally launched this week at DAC, are about to flow from several working groups.

"A whole pipeline of specifications are in the works for the next few months," said Doug Fairbairn, president of VSI. "People will see tangible solutions in the form of these specs."

Perhaps most hotly awaited of the new specs will be the definition of three interfaces from a working group studying on-chip busses. A spec for a peripheral interface should be released for general review by September. Two specs representing two different flavors of a systems-level interface should be released by the end of the year.

The physical and register-transfer level interfaces are key standards for linking intellectual-property cores. VSI expects companies to develop "wrappers" that would encapsulate their specific on-chip buses in a way that links to the VSI interfaces.

Separately, a VSI working group on system-level design issues is expected to release guidelines this fall for the kinds of behavioral models to be used in defining systems chips. A subgroup trying to define model-level interfaces — so that information could be shared between various models — expects to release initial results of its first efforts sometime next year.

Among other moves, VSI is close to releasing a white paper which will recommend ways of providing security for intellectual property. And guidelines for dealing with soft IP cores are expected to be released later this year as a second phase of work from an implementation/verification group. The soft core guidelines are facing significant debate at the moment because they include a separate debate over standard library formats that has positioned the ASIC Council's OLA proposal against the .lib format of Synopsis.

"All of the working groups are in a stage where we will begin to see results from them soon," promised Larry Rosenberg, a consultant and technical committee chairman for VSI.

Gaping holes
Based on presentations from a range of panelists at a forum sponsored by VSI, the magnitude of the system-chip challenge is casting a significant shadow on VSI's efforts.

"If we could get all the RTL we needed instantly and for free, we would still not be able to meet our time-to-market objectives," said Terry Thomas, managing director of strategic alliances and design systems for Nortel Semiconductors (Nepean, Ontario), part of Northern Telecom.

Thomas lobbied for greater availability and support for customer-owned tooling as a means to merge a systems company's intellectual property strengths with a necessary understanding of the physical characteristics of process technology. "You don't need to give away your IP to get good manufacturing services, but that's what we have been doing frequently in the past," said Thomas.

The Nortel manager also raised unresolved business and legal issues on the road to system-level chips. "There's no advantage to replacing three man-years of technical effort with four man-years of legal effort," he quipped, adding that Nortel's goal is to leverage its own systems expertise as much as possible for legal and reliability issues. "I would no more buy IP from a two-person startup than I would buy a VCR in a bar," he joked.

In a separate presentation, Scott Eisenhart, manager of ASIC library development and design reuse at Texas Instruments Inc., addressed the difficulty of defining an on-chip interface that would link virtual components. "We have not been able to get to the point where we can offer standard interfaces that make everyone happy," he said.

Eisenhart described the design process TI has developed to reuse its DSP cores and peripherals in applications-specific designs. Separating a payload from the specific interface is one answer TI sees to the on-chip interface issue, he said. TI is also participating in work to develop a System-Level Design Language, he added.

"Hardware description languages cannot serve the needs of embedded software for various processor cores," warned Ivo Vandweerd, business development manager for Easics (Leuven, Belgium), who described his company's methodology. "We need a unified representation of hardware and software," he said.