SAN FRANCISCO — Looking to fill the market vacuum for RF design tools, two companies told the 35th Design Automation Conference last week of their development work on advanced simulators and layout tools for RF ICs.

Bell Laboratories, the research arm of Lucent Technologies (Murray Hill, N.J.), said it has developed a simulation tool set that is dramatically faster than current harmonic balance simulators used for RF circuit analysis. The tools could be the first to perform full-chip simulation on RF ICs. And separately, Hewlett-Packard Co.'s EEsof Division quietly disclosed that it is developing a design tool specifically geared toward gallium arsenide (GaAs) ICs.

The CAD tools in development at Bell Labs are intended for a new generation of RF ICs, said Peter Feldmann, distinguished member of the lab's technical staff. With higher integration, the circuits will include a greater number of circuit elements, which will press frequency-domain simulators to model a higher number of non-linear elements, and time-domain simulators to model multiple time scales. Current harmonic balance simulators can model two- or three-transistor RF circuits, Feldmann said. "They will break when you get up to 10 transistors," he said.

Harmonic balance simulators, which examine propagated signals in the frequency domain, were long "blacklisted" by RF IC designers for their inability to handle non-linear circuit elements, said Feldmann. Frequency-domain simulators are also hampered by their inability to describe what Feldmann calls "non-sinusoidal" events — square-wave pulses and transients. Time-domain simulators, such as Spice, on the other hand, are useless at describing the interaction of signals at widely disparate frequencies. A typical example is in cell phones, where a 1.2-MHz CDMA voice modulation scheme is superimposed on a 1.9-GHz RF carrier. The time-domain simulator cannot analyze both signals in the same run, Feldmann said.

Researchers at Bell Labs developed algorithms that effectively streamline the calculations for both harmonic balance and time-domain simulators. Linear algebra is used to reduce the computation matrix for the frequency-domain simulation, and multiple time steps are used to speed-up the time-domain calculations. Also, the algorithms extract fairly compact linear models from an RF circuit. The result is a two- or three-order-of-magnitude speed up in simulation speed, he said.

The tool set was used to simulate a Lucent GSM chip set that included a mixer, local oscillator and low noise amplifier (LNA). While the simulation took over a day to generate results, current-generation harmonic balance simulators could not have handled such a large simulation, Feldmann said. While there are no announced plans to productize the simulators, Feldmann said Lucent's Design Automation Group has "strong interest" in his work.

Also at DAC, HP EEsof revealed progress on its Advanced Design System, a tool set that combines EEsof's RF and microwave design tools (including harmonic balance simulators) with DSP algorithm development tools. "RF design is generally segregated from other parts of the design," said Todd Cutler, product marketing section manager at EEsof, "but 40 percent of design work is now devoted to integration." HP hopes to add data flow simulation, DSP instruction set simulation, photonic system design (which simulates the interaction of lasers, fiber optic cables and receivers, and can be useful for transoceanic cables), and new RF IC and RF board layout tools to the design system.

Cutler acknowledged that HP is developing an active physical device simulator for GaAs circuits. This system leverages the results of research conducted by HP under the auspices of the Microwave and Analog Front-End Technology (Mafet) program funded by the Defense Advanced Research Projects Agency. Ideally, the GaAs device simulator would yield fast results for newer, more integrated devices.