SAN FRANCISCO — An industry grappling with system-on-a-chip design challenges will find some answers later this month as developers, researchers, managers and engineers from across the globe converge in San Francisco for the 35th annual Design Automation Conference. Roughly 20,000 attendees are expected to visit the Moscone Center during the show's June 15-19 run.

Chaired by Basant Chawla of Lucent Technologies, the 35th-anniversary show promises greater semiconductor-vendor participation and progressive design and tutorial tracks. More than 170 exhibitors, including many startups, are expected to show solutions for logical and physical design.

On June 14 (the Sunday before the main show's opening), DAC will offer its third annual women's workshop, running from 9 a.m. to 4 p.m. This year's workshop, "Forget the Ceiling — Break the Glass," is designed to help women develop a personal plan for career development. The event will be chaired by Simplex president and chief executive officer Penny Herscher and is divided into five sessions.

Nora M. Denzel, senior vice president of Legato Systems Inc., will kick off the sessions with a keynote titled, "Top 10 Ways Women Shoot Themselves in the Work Force." The workshop will also include a panel session on the habits of highly successful women, a tutorial on mentoring, a workshop on identifying changes you can make to break your personal ceiling, and a speech called "Breaking Records through Visualization" by three-time Olympic trialist and Cadence group director Barb Acosta.

On Monday, June 15, DAC will host its exhibitor-presentation marathon, during which each exhibitor — EDA vendor, semiconductor company and core vendor, alike — will have 20 minutes to explain its business and what it is doing at the show. The session will run from 9 a.m. to 6 p.m., with more than 130 companies in six concurrent tracks scheduled to offer presentations. Monday will also feature free admission to the exhibit floor and the DAC debut of Silicon Village, where semiconductor and core vendors will show their wares.

The 35th DAC will feature two program tracks, each running from Monday through Wedensday. The tracks will be spread over five concurrent sessions. The Design Methods track will target designers, offering sessions on such topics as formal verification, hardware/software codesign and deep-submicron design. The Design Tools track will address EDA researchers. Topics will include design reuse, timing analysis and logic optimization.

The 35th DAC will feature two keynotes. On Tuesday at 9 a.m., William Spencer, chairman of Sematech Inc., will deliver the opening keynote, "Design Automation Can Help the Semiconductor Industry Address its Many Challenges." On Thursday at 1 p.m., keynote speaker George Heilmeier, chairman emeritus of Bellcore, will deliver "From POTS to PANS: Transition in the World of Telecommunications for the Late '90s and Beyond."

This year, DAC has modified its lunchtime executive panel to include customers and members of academia as well as EDA executives. Scheduled to start at 10:30 a.m. on Tuesday, the panel will be chaired by Thomas Peninno of Lucent Technologies and will include the University of California-Berkeley's Robert Brodersen, Alcatel Microelectronics' Johan Daneels, Intel's Gadi Singer, Synopsys' Aart de Geus, Cadence's Jack Harding and Mentor Graphics' Wally Rhines. The panel will discuss the future of EDA.

Other Tuesday highlights include the debut of the "University Design Contest," which promises to present the best in university-developed electronic designs and methodologies, and a DAC-sponsored cocktail party. A panel comprised mostly of users will discuss noise problems in deep-submicron ICs.

Wednesday's session highlights will include a panel session called "How Much Analog Does a Designer Need to Know for Successful Mixed Signal Design?" and another called "User Experience with High-Level Verification."

On Wednesday night, starting at 7:30 p.m., all attendees are invited to the "35 Years of DAC Anniversary Party."

Thursday's lineup will include a panel called "Design productivity: How to Measure it? How to improve it?" and one called "The EDA Startup Experience: The First Product." Sessions will probe interconnect analysis and reliability in deep submicron, as well as functional verification for complex ICs.

The entire series will wrap up Thursday evening with a grand panel session called "Thirty-Five Years of Design Automation: a Retrospective and a Look Forward." Chaired by Intel's Paul Weil, the session will gather industry veterans Ron Rohrer of Intersouth Partners, Bryan Preas of Xerox Parc, and U.C. Berkeley professor Alberto Sangiovanni-Vincentelli, who will review the accomplishments of the past 35 years and share their views on the future.

Friday will feature six all-day tutorials: "Design Validation Techniques," "Design of Complex Mixed-Signal Systems on a Chip," "CAD for System Design," "Interconnect Analysis in High-Frequency Submicron Digital VLSI Design," "Finding Errors and Locating Defects" and "High Performance RTL Coding Styles for Synthesis."