SAN FRANCISCO — A milestone in design verification was reached at the 35th Design Automation Conference as Synopsys Inc. (Mountain View, Calif.) and Quickturn Design Systems Inc. (San Jose, Calif.) set aside their rivalry to combine hardware/software coverification with emulation. They also announced completion of work to link synthesis more closely to emulation.

Coverification tools such as Synopsys' Eagle link software-debugging tools, such as instruction-set simulators, with HDL simulation. The chief bottleneck is that HDL simulation runs far slower than software-debugging tools. If an emulator handles the HDL portion of the design, that bottleneck disappears.

Synopsys and Quickturn will tie Eagle to Quickturn's System Realizer, Cobalt and Mercury products. "What you're getting with these two capabilities is the first fully contained design-verification environment in the industry," said Keith Lobo, president and chief executive officer of Quickturn. "This allows hardware/software codesign at a performance level never possible before. It may be the catalyst that makes codesign a reality on a mass scale."

Lobo said combining Eagle with Quickturn's Mercury reconfigurable-computing product is especially advantageous, given Mercury's ability to accelerate event-driven Verilog simulation as well as provide register-transfer level and gate-level emulation.

"An emulator from our perspective is just an awesomely fast simulator," said Aart de Geus, chairman and chief executive officer of Synopsys. He noted that the first step, which has already been taken, is to link Eagle to Quickturn emulators through existing application programming interfaces. Follow-up work, he said, will provide "more direct access."

The initial integration with Eagle has been carried out through Quickturn's Q/Bridge cosimulation interface.

Tighter synthesis link
Meanwhile, Synopsys and Quickturn announced they have completed work, which was announced last year, to tie synthesis more closely to Quickturn's System Realizer and Cobalt emulators. The 1998-08 version of Synopsys' Design Compiler adds a Quickturn-specific configuration that automatically sets up the necessary optimization parameters for targeting designs to emulation during synthesis.

Quickturn is also supporting Synopsys' ".lib" ASIC library format and Stamp format for intellectual-property modeling.

Synopsys recently announced the linkage of Eagle to its own Cyclone cycle-based VHDL simulator. The combination was used to verify a 5.5-million-gate, 24-processor network switching system at Siemens Public Communications Networks.

Mentor Graphics Corp. (Wilsonville, Ore.) had previously linked hardware/software coverification to emulation. But Quickturn is the overwhelming market leader in emulation. Further, because of a patent dispute with Quickturn, Mentor is currently barred from selling its emulator in the United States.