SAN FRANCISCO — Facing an increasingly difficult market, silicon vendors are turning to any alternative to improve the utilization of their existing resources, and stave off the need for capital investments. This was illustrated yesterday by a joint announcement from library-architecture designer In-Chip Systems, Inc. (Sunnyvale, Calif.) and the Sony Corp. of Japan.

Sony, a previous licensee of In-Chip's 0.25-micron cell architecture, has signed a second license with In-Chip, this time for the very mature 0.35-micron process.

The reason for the new license was interesting, according to In-Chip president, Tushar Gheewala. He explained that the In-Chip architecture, which serves as a basis upon which to build gate-array or standard-cell libraries, can reduce die area on the order of 30 percent on a given process compared with libraries built with conventional layouts. This shrink also results in an average 20 percent reduction in the length of metal runs.

Sony, Gheewala said, was appreciative of the speed and power improvements from the new libraries, but was primarily after a different goal altogether. The die shrink that comes with the In-Chip architecture permitted them to do some critically needed load-balancing between ASIC and application-specific standard product chips, significantly improving the throughput of the 0.35-micron line.

The better utilization of an existing line justified the move to new libraries, according to Gheewala. Thus an architecture developed to meet the challenges of deep-submicron interconnect design turned out to have an important application in coping with the weakened semiconductor market.