PADERBORN, Germany — Incases Engineering GmbH has enhanced its two main printed-circuit-board design platforms, EMC-Workbench and the Theda PCB design software, in time for demonstration at the Design Automation Conference.

EMC-Workbench, Incases' signal-integrity and crosstalk-analysis software for digital interconnect, now has an additional software module called Batch Signal Integrity. The module provides a detailed signal-integrity simulation of complete pc-board layouts or large sections of a layout, and is intended to be a "golden simulator" for pc-board signal integrity and timing sign-off prior to manufacturing.

Batch Signal Integrity uses the same non-linear reflection and crosstalk simulator, known as Freacs, used for online simulations within EMC-Workbench, but operates on all nets without user intervention and presents data in a spreadsheet format. The results are summarized by net in a tabular format with a column for each of 25 signal-integrity and timing characteristics.

In contrast, Freacs operates interactively on single nets and shows results in a waveform window.

Although it may take several hours to complete its run, Incases claims the batch software simulates all digital interconnect paths and achieves 100 percent coverage of all digital signal paths in most cases. Exceptions include instances where a bus may have multiple possible drivers and receivers creating a very high number of possible instances to simulate.

Prior to its use, Batch Signal Integrity provides an estimation of the time and memory resources required to complete the simulation, and the user has the ability to interrupt and resume the simulation process. Interconnect delays are quantified and can be passed, in SDF (Standard Delay Format) files, to logic.

The batch tool also provides automatic generation of project documentation, which often takes up to 30 percent of the analysis time. "It may sound really boring, but it is probably the biggest time saving we can provide for engineers," said Peter Wolfers, vice president of marketing at Incases Engineering.

The introduction of Batch Signal Integrity is part of a number of enhancements made within Version 4 of EMC-Workbench being announced at DAC.

Version 4 will also integrate EMC-engineer, previously a standalone EMC screening tool. It will improve radiation analysis and automate project documentation.

For radiation analysis, the 3-D simulation kernel and the algorithms for dividing copper areas into an analysis mesh have been changed to provide increased accuracy, while reducing simulation time when simulating complex signal and return paths. In addition, new field-scan types , including cylindrical and spherical field scans, provide alternative ways to display and view data.

"Through the use of new, intelligent copper-area discretization algorithms, we are able to reduce the number of mesh elements, while not impacting accuracy, providing our users with a net performance gain of approximately 30 percent when working on this type of structure," Wolfers said.

EMC-Workbench is available in several configurations, on Unix and Windows NT, from approximately $20,000.

Gridless placement
CE-Placer is a so-called gridless component-placement tool suite for use with Incases' Theda PCB 6.0 design system. It will be available at the end of September, along with the release of Theda 6.0.

The new tool operates in three ways: whole-of-board, constraint-based simultaneous placement; sequential placement; and a through a set of optimization processes that can be used with either or both of the primary placement techniques.

According to Incases, the constraint-based simultaneous placement function is able

to resolve the placement of many hundreds of components, and their attached electrical and manufacturing constraints, within seconds. The constraints will typically include nominated fixed components, signal integrity, minimizing interconnect and avoiding resonant interconnect lengths. The board edge is also used as a source of "tension" in the solving algorithm.

Although an initial simultaneous placement may produce conflicts, such as overlapping components, the software will automatically divide the board down into sub-areas to resolve conflicts and produce a final placement.

Sequential placement is used for completing placement on very dense boards where components can be inserted between existing components, while ensuring no constraint violations. Engineering constraints are used to control placement and to ensure that new violations are not introduced.

Typically, sequential placement would be used to insert decoupling capacitors between ICs, following the placement of all major components using simultaneous placement.

The optimization process can perform a number of functions on the placement such as adjusting to bring the components into line for manufacturing considerations. A placement compactor is similar to compactors used when laying out large ASIC designs. The compaction function attempts to improve the resolution of the engineering constraints and reduce the overall length of the routes.

"Typically, the user of these new tools would use both the global and sequential placement functions to quickly place the board," said Reinhard Wiedenmann, vice president for Theda R&D at Incases. "They would then optimize them semi-interactively to achieve final placement."

CE-Placer is listed at $8,500 for either Unix or Windows NT.