PALO ALTO, Calif. — With a significant expansion of its Vera environment for test-bench generation, Systems Science Inc. (SSI) has entered the VHDL market and become a hardware/software coverification provider. The new product, Vera-SV, also adds automatic stimulus generation, dynamic coverage feedback, self-checking through "data agents" and distributed processing.

The original Vera product is essentially a language for constructing Verilog test benches. "Vera is being used successfully, but people have been coming to us saying they want to verify complete systems," said Ghulam Nurie, SSI's vice president of worldwide marketing. Vera-SV, he said, can do so because it covers hardware, software and test benches.

Vera-SV is also the first SSI product to support VHDL test-bench generation, using the same language-neutral environment as Vera. But because there is no standard VHDL programming language interface (PLI), specific simulators must be supported, and SSI is starting with Model Technology's VHDL simulator. Vera-SV works with all simulators that support the standard Verilog PLI.

The Vera hardware-software coverification module lets designers run their software drivers, diagnostics or applications on a workstation or PC, interacting with hardware described in Verilog or VHDL. The user can connect the lowest-level software I/O with hardware model pins, and control the synchronization granularity.

In essence, said Nurie, Vera-SV replaces calls to operating systems with calls to Vera functions. Low-level I/O on the Vera side provides the connection to the HDL environment. Users can run third-party software compilers or debuggers at full speed.

Unlike coverification systems from providers such as Mentor Graphics Corp. or Synopsys Inc., Vera-SV requires no processor models. That's because it's working at a higher level of abstraction, before machine code is generated. Drivers don't need processor models, Nurie said, and applications don't either until machine code is compiled. At that point, users would need to turn to a system that includes processor models. Vera-SV doesn't support the use of real-time operating systems or instruction-set simulators.

The automatic stimulus-generation module can produce random, constrained random and directed functional tests. Vera previously allowed only programmatic test generation, but Vera-SV has been enhanced to permit declarative test generation. That provides an easier way of developing many kinds of tests, such as sending streams of packets to exercise characteristics of a switch.

The dynamic-coverage feedback module monitors the test-bench generator and the design under test, and uses the information to guide test generation. It supports user-defined coverage blocks, allowing, for example, designers to look at how many times a register is changing in value.

SSI provides a query language that lets users customize the coverage. For example, a user could write a query to generate a cross-coverage report for two coverage objects, showing the simultaneous transitions covered by two interrelated state machines.

The module is quite different from commercial code-coverage tools, Nurie said, because it's not just looking at HDL lines — it's checking functional "objects" such as states and registers. In addition, users can run the coverage on the test bench itself without running any simulation.

Vera-SV lets users establish data agents that check the test itself, rather than the design. This provides a self-checking capability that can make it easier to interpret simulation results. "The big gain is that you don't have to look at simulation waveforms to see if tests have passed or not," said Nurie.

Finally, distributed processing allows users to run multiple tests over a heterogenous network, or even to partition a design, if there are natural boundaries. Software and HDL simulation can be executed on different processors in a network.

Vera-SV is available now on Unix platforms. The price ranges from $12,500 to $32,500.