SAN FRANCISCO — A panel session on how to measure and improve design productivity, held on the final day of the 35th Design Automation Conference, turned into a debate on whether the greatest improvements will come from methodology or EDA tools.

While some said that it was not up to an ASIC design team to develop tools, and they should therefore concentrate on improving methods, others emphasized that methods alone could not yield the looked-for improvements in design productivity. It was also revealed that among the world's leading semiconductor companies, design productivity varies by a factor of ten or more.

Andy Becholtsheim of Cisco Systems (San Jose, Calif.) observed that with more than 50 percent of the time being spent on verifying designs, verification is the bottleneck in design at the moment. Simulation, which needs to be speeded up by a factor of 100 to 1,000, is also a problem area. Although, he said, such a speed-up was theoretically possible with the application of additional hardware, so that simulations can run on workstation farms. "Tools are coming which are expected to dramatically speed up the back end," he said.

Chris Clucas of the Design Services division of Cadence Design Systems Inc. (San Jose, Calif.) said, "We are very aware of design productivity because that's what we get paid for." He observed that design productivity is a function of people, tools and methodology, and went on to say that of these three, the most important is methodology. He elaborated by discussing a triangle of influence. At the top, company-wide changes can produce a factor-of-ten improvement; divisional changes result in a factor of two; while changes implemented only at the engineering-management and design-engineer level are of marginal benefit.

Ron Collett of Collett International Inc. (Santa Clara, Calif.), an organizer of the panel session as well as one of the panelists, discussed attempts by his company to find a quantifiable metric of design productivity.

Collett said, "All transistors are not equal in difficulty, therefore there is a need to measure the [design-in] complexity of each transistor." He came up with the following formula: design productivity equals normalized transistors, divided by effort that's measured in person-weeks.

Without detailing how Collett International "normalizes" transistors, he drew on a study of 21 chip designs from 14 leading semiconductor companies conducted by his company in 1997. This showed that the relative productivity of the top company was fourteen times that of the least productive. The companies surveyed included Intel, Texas Instruments and others, although the results were shown anonymously.

Collett also revealed that one of the design teams still used schematic entry to capture designs rather than a hardware description language, and yet was not the least productive.

Jim Thomas of Motorola's M-Core Technology Center in Austin, Texas, characterized the current situation as being similar to the children's tale of "Chicken Little," in which an inexperienced chick goes around saying, "The sky is falling, the sky is falling," and solicits help to spread the word. The result is despondency among those who should know better.

Thomas observed that going as far back as the 1970s, microprocessor design teams in Motorola have stayed at about 60 to 100 people and produced exponentially more complex designs in terms of transistor count. The implication was that engineering ingenuity would find a way to continue that increase, although the makeup of design teams is shifting to emphasize verification.

Thomas also feels that it is the measure of transistors per designer-day that may be out-dated, having been rendered relatively meaningless by changes in ASIC design style, reuse, and a move up to block-level design. He postulated that revenue per engineering year as well as percentage reuse will be important measures in the future.

Chris Malachowsky of Nvidia Corp. (Sunnyvale, Calif.) said that the best top-level measure is time-to-revenue, as this encompasses hardware, software and documentation. "Be careful what you measure-because that is what you will improve," he warned.

In response to the prompting of panel chairman Carlos Dangelo from LSI Logic Corp. (Milpitas, Calif.) to discuss how to improve designer productivity, his LSI Logic colleague Jeff Hilbert said, "Stay away from the technology and concentrate on people methods and experience." To which Becholtsheim responded, "But tools are the encapsulation of skills and processes, and the means to spread them throughout the team." He added, "We need better tools. People don't give you 100 percent improvement per year."

Malachowsky came down firmly in the Becholtsheim camp when he said, "Reward results, not effort. Then some people work harder, some people work smarter-and some people develop tools. I am a lazy engineer. I like CAD."

Collett pointed out that regardless of whether or not better tools are developed, there were major gains to be made by adopting the best practices in design methodology. "In our study, there were no big differences between the tool sets, and the best was 14 times better than the worst." He added: "I believe we're only going to see incremental improvements in tools."

But Becholtsheim was more optimistic on the tools front. "I've been looking at [EDA] start-ups-it seems about 100 must have got started in the last year. A lot of the assumptions we have from the established EDA companies are just plain wrong. Processes that we thought [would] take days can be compressed to minutes."

The panel reached no consensus, implying that both methodology and new tools will be important in the effort to sustain traditional improvements in design productivity.