Posted: 3:00 p.m., EDT, 6/29/98

RICHMOND, Ill. — A new type of high-level modeling tool, X-CDE (pronounced "exceed") from X-Tek Corp., promises a graphical alternative to behavioral HDL design. The tool offers design entry, transaction-based simulation, performance modeling and automatic generation of synthesizable HDL code.

X-Tek first appeared last year with X-HDL, a Verilog-to-VHDL bidirectional translator. Thomas Rock, founder and chief technology officer, was a consultant with Mentor Graphics before starting the company, and has worked in digital design at Delco and Honeywell.

X-CDE is based on "place/transition" modeling technology, which was developed at the University of Aarhus in the Netherlands to model various kinds of abstract processes. It's particularly well-suited for systems that contain a number of concurrent processes that communicate and must be synchronized. The methodology provides a graphical representation and formal analysis techniques.

This modeling technology isn't specifically aimed at electronic design, however, so X-Tek's work has involved tailoring it to that purpose. The initial release of X-CDE is aimed at digital hardware design, but later releases will support hardware/software codesign and allow analog modeling.

"With HDLs, people are fighting with the language itself," said Rock. "X-CDE makes it easier for the designer to design, and gives him more power to do things easily."

Current high-level design tools are usually aimed at functional design, which has to do with defining algorithms, or architectural design, which analyzes system resources and looks at issues such as throughput. Rock said X-CDE is closer to the architectural side but "blends over" into the algorithm-development space.

Unlike most high-level design tools, which tend to be specific to a domain such as DSP, X-CDE claims to offer a solution for all design domains. X-CDE does not come with any domain-specific library support.

To use X-CDE, designers first build a graphical diagram using three types of symbols — places, arcs and transitions. Users can add scripts in the current release and will be able to import VHDL or Verilog in a future release.

Places, represented graphically by circles, hold one or more "tokens" of information. This information can be anything — Boolean, integer, real, user-defined quantity, array, data structure or an object. For RTL designs, places can hold only one token at a time.

Transitions, represented graphically by rectangles, define when tokens can move in the system. Arcs, represented by directed lines, connect places and transitions and define the movement of tokens through the system.

One a design is defined graphically, users can invoke the simulator, which displays the simulation state directly on the diagram and also provides waveforms. User-defined breakpoints allow dynamic control. Designers can use stochastic modeling to probe such issues as throughput.

X-CDE also has a built-in formal-verification engine that performs model checking. It can probe all possible states in a model and verify properties such as "liveliness," which flags states that cannot be exited. Users can add their own queries through a menu or through text. A later release will provide formal equivalency checking between two state graphs at different levels of abstraction.

Using simulation and formal verification, users interactively refine their diagram until it reaches a register-transfer level of abstraction. Only then can X-CDE generate code that an RTL synthesis tool can understand. X-CDE doesn't provide automatic behavioral synthesis, but it offers an environment in which users can do their own scheduling and resource allocation.

The tool also claims design security features not available with a language-based approach. For example, a design can be set to a "read-only" mode in which it cannot be modified, or an "analyze-only" mode in which it cannot be viewed.

X-Tek is shooting for production shipment in August on Unix and Windows NT platforms, with prices starting at $25,000.