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We'll be posting stories throughout June on announcements and activities coming out of the 35th Design Automation Conference, scheduled for June 15-19 in San Francisco. Stop back to find the latest news. |
Week of May 25, 1998
Interra to roll out synthesis engine, net-list object model (3:00 p.m., EDT, 5/29/98)
'Formal synthesis' tool adds a pioneering spin (3:00 p.m., EDT, 5/29/98)
VeriBest rolls out multi-tiered PCB tool suite (3:00 p.m., EDT, 5/29/98)
Sente tool for power analysis achieves new 'peak' (3:00 p.m., EDT, 5/29/98)
Xynetix BGA tool gets autorouter (3:00 p.m., EDT, 5/29/98)
Viewlogic's Motive gives way to 'Blast' analyzer (3:00 p.m., EDT, 5/29/98)
Tool assists package design (3:00 p.m., EDT, 5/25/98)
Week of May 18, 1998
Reconfigurable-computing engine attacks verification bottleneck (11:45 p.m., EDT, 5/22/98)
Noise-analysis tool bows for deep-submicron (3:00 p.m., EDT, 5/20/98)
Two vendors push FPGA tools into ASIC domain (7:00 p.m., EDT, 5/18/98)
Verplex joins the formal field (7:00 p.m., EDT, 5/18/98)
Tools target wire harnesses (3:00 p.m., EDT, 5/18/98)
Mixed-language simulator addresses diverse IP (3:00 p.m., EDT, 5/18/98)
Startup Moscape offers 'assertion-based' analysis (3:00 p.m., EDT, 5/18/98)
PADS takes interconnect tool into BGA arena (3:00 p.m., EDT, 5/18/98)
Week of May 11, 1998
Tera Systems touts structured-ASIC design (3:00 p.m., EDT, 5/11/98)
Transistor-level layouts targeted (3:00 p.m., EDT, 5/11/98)
Week of May 4, 1998
Startup Aristo pioneers 'block-level' EDA (3:00 p.m., EDT, 5/4/98)
Week of April 27, 1998
TauSim, a Verilog simulator newcomer, pushes speed (3:00 p.m., EDT, 4/30/98)
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