Building system-on-a-chip designs
By Richard Goering and Peter Clarke
Strides in systems-on-a-chip design are compelling the semiconductor and EDA industries to overhaul design methodologies, tools and even business and legal models as engineers struggle to shrink the contents of today's printed-circuit boards onto tomorrow's silicon substrates. In this report, EE Times looks at three major aspects of systems-on-a-chip design and their effect on designers and tool developers.
First, system-level definition must be carried out with more rigor and organization than in the past. The emerging System-Level Design Language (SLDL) will help with that effort, as will nascent technology in hardware/software codesign and DSP algorithmic design.
The second aspect is the creation of reusable intellectual-property (IP) blocks, or "block authoring." Large system-design companies are inventing new organizational structures and standards to achieve design reuse. Synopsys Inc. and Mentor Graphics Corp. have co-authored a "Reuse Methodology Manual" to help designers with block authoring.
Third is the assembly of existing IP blocks, or "block integration." An "integration platform" can help define the hardware and software architectures into which the blocks must fit. Software debugging for embedded cores and design reuse through layout migration are two challenges for block integrators.
A final point to remember is that systems-on-a-chip may involve far more than just digital logic. Therefore, this report also examines special considerations for mixed-signal blocks and for micro electro mechanical systems (MEMS) on system-level chips.
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