In the fall of 1996, while members of a panel at the EuroDAC meeting , Mentor Graphics chief executive officer Wally Rhines and Synopsys chief executive officer Aart de Geus had a conversation that led to one of the most significant efforts in enabling design reuse. The result was the just-published Reuse Methodology Manual.

At the time, both Rhines and de Geus were in the midst of creating their company strategies for making their customers successful in system-on-a-chip (SOC) design but each faced different challenges. Synopsys Inc. had stopped selling the initial version of its Peripheral Component Interconnect bus (PCI) macrocell and was deeply involved in redefining its design methodology to ensure the success of its subsequent intellectual property (IP) blocks. Mentor Graphics Corp. was on its way to becoming one of the leading IP providers, but was facing challenges in readily obtaining high-quality IP blocks from third-party suppliers. In the course of their conversation, the CEOs realized that to make design reuse a reality and SOCs possible, the industry needed some clear guidelines on IP creation and deployment.

The industry itself was becoming more aware of the challenges of design reuse and that same fall (1996) the Virtual Socket Interface (VSI) alliance was formed. Its charter was to enable the mix and match of IP blocks by defining, developing, authorizing, testing and promoting open standard specifications relating to data, formats, test methodologies and interfaces. Mentor Graphics and Synopsys were founding members, but both saw that there were many problems with IP creation and deployment that VSI would not address.

About nine months later at the 1997 Design Automation Conference, Synopsys and Mentor Graphics announced a partnership to promote design reuse as an essential component of SOC design. Through the Design Reuse Partnership, the companies committed to make reuse a reality by providing predictable yet portable high-quality IP blocks, IP creation tools and IP creation methodologies to design teams worldwide. More importantly, the companies committed to jointly writing the manual, a 225-page book that describes the methods, standards and procedures necessary to create and successfully use IP blocks and that is now available from Kluwer.

Though driven by different experiences, both companies had arrived at the same conclusion: the current procedures and standards that drove IP creation and design reuse were woefully inadequate. Both companies, like many of their customers, realized that the only way to keep up with the unforgiving escalation of Moore's Law (the number of transistors that can fit on a chip will double every 18 months) was to develop a systematic design reuse strategy. Unfortunately, when these customers investigated commercially available IP blocks or tried to develop their own, they found that the ad hoc engineering practices that were commonly used to build reusable blocks were often totally inadequate.

Design teams attempting to practice design reuse were finding that developing and implementing IP blocks wasn't as easy as it first appeared. At the heart of this problem were two concerns: quality and ease of use. First, they found that quality IP blocks must be bug free and that exhaustive verification was mandatory to keep IP blocks truly usable and reusable. Second, IP blocks must be flexible enough to span a variety of different applications.

For example, PCI IP blocks must be able to accommodate the 32-bit and 64-bit configurations of the standard, as well as 33-MHz and 66-MHz bus speeds. Truly flexible IP blocks must also accommodate different platforms, design methodologies and verification environments. As a result of these shortcomings, Synopsys and Mentor Graphics decided to pool resources to solve the very real problems associated with implementing a practical design reuse strategy. Both companies saw that solid reusability guidelines would benefit their customers and the industry at large by providing instructions for the creation and integration of IP blocks in future designs. Thus the idea for a reuse partnership was born.

In 1992, Synopsys was developing its own libraries of small reusable components such as adders, multipliers and other relatively simple devices. These components, called the DesignWare Foundation Library, were a precursor to larger, more complex IP blocks, but were primarily an extension to Synopsys' Design Compiler product. Synopsys used this effort as a springboard and in 1995 introduced its first real IP block, a PCI core. Like other vendors in the burgeoning IP market, Synopsys had success in selling the core, but customers found significant challenges in using it successfully: meeting timing constraints was the main challenge. This was caused by insufficient testing in multiple technology libraries. In an effort to deliver on its customers' demands, Synopsys built a large number of parameters into the first version of the PCI macrocell. In the end, they made it hard to configure and led to a number of functional bugs. Although the core did not require user modification, its 192 parameters resulted in an intractable verification problem.

Eventually, Synopsys pulled the PCI core from the market. The reason was simple. In order to successfully tailor it to every customer's design, a significant amount of on-site support was needed. Clearly, this wasn't a practical way to do business. Other vendors were investing in large support services so this first-generation IP block was saddled with the reputation of being difficult to use and sometimes simply not worth the effort. The DesignWare team decided to determine exactly what was required to deliver cores of high quality, that were easy to use and realized the promise of reuse.

One of the first things that the team had to recognize was that IP blocks are very different from EDA software. Traditionally, EDA customers demand the most advanced algorithms in EDA software to allow them to make bigger, faster chips in the least time. Quality and ease-of-use concerns are secondary because customers would rather work around those problems in order to get early access to the tools. IP blocks, however, are different. If the block is not bug free, the end product simply won't work and the product cannot be shipped. Workarounds and other solutions are not readily available and often come too late, after a design is committed to silicon. Without ease of use, it is simpler for customers to design their own. Realizing this, the DesignWare team added a number of engineers and managers with extensive ASIC and system design experience.

During this period, the DesignWare team was focused on the PCI core but had to keep adding components to the DesignWare Foundation Library and macrocell product line. To do this, they enlisted third-party designers to develop blocks for them. They quickly found that these designers needed clear and unambiguous descriptions of the deliverables and verification methodologies required. If these guidelines weren't supplied, the DesignWare team ended up substantially redesigning the components. At the same time, Synopsys saw that the IP industry was heating up and decided to look into obtaining IP blocks from third parties. Unfortunately, much of the commercial IP then available was of unacceptable quality and suffered from the same sorts of problems as the first version of Synopsys' PCI macrocell. Though many of these problems were being addressed by third-party IP providers, it was clear that collecting reusability guidelines in a coherent manner could only accelerate the adoption of sound design reuse and IP development practices. As a result of these experiences, Synopsys developed the Sourcing Handbook, a document that described in detail the deliverables and design methodology for both DesignWare Foundation Library components and IP blocks to be developed by third parties and sold by Synopsys.

While the company researched and documented its methods for developing IP blocks, it also started designing the DesignWare DW8051 macrocell, a synthesizable 8051 microcontroller. It became clear that more than an exhaustive description of deliverables and methodologies was required. A document would be needed that described how to create cores that were of excellent quality and were easy to use. The result was called The Style Guide, which later became a seed document for the synthesis portion of the new manual. The idea behind the guide was simple: to describe those basic principles of good design that many engineers were taught in school, but which were violated in all the IP blocks that the DesignWare team reviewed. The team discovered a consistent pattern to the problems in commercially available IP blocks.

First of all, the design representation was not appropriate. For example, the RTL might be available in Verilog but not in VHDL, or a gate-level netlist using a 0.5-micron library was available, but an incompatible 0.35-micron library was now being used. Often, the design came with incomplete design information, with no functional specification and with unreadable, uncommented code. Supporting scripts were not available or were so obtuse as to be unusable. In some cases, the full design was never properly archived, so pieces of the design were scattered over various disks on various machines. Sometimes the tools that were used to develop the design were no longer supported or their vendors were out of business. Often, the tools used to develop the design had poor interoperability and the scripts used to patch the tools together were missing. Finally, even if a hard macro was available, the simulation model was often so slow that system-level simulation was not practical.

During this same period, Mentor Graphics was developing its IP Division, called Inventra, which was a natural evolution of the company's long history in IP. For more than a decade, Mentor Graphics had been producing and maintaining IP libraries as an integral part of its ASIC and IC design automation environments. This experience sensitized Mentor Graphics to the importance of consistency and compatibility in the production and delivery of IP blocks.

In starting Inventra, Mentor Graphics now had the additional challenge of assimilating IP blocks from external sources that were brought into the company through acquisition. These included 3Soft with its microcontroller cores, Systolic with telecommunications technology, dQDT with DSP cores and CAE Technology with peripherals.

While consolidating these divergent IP sources into a single product line, Mentor Graphics found itself dealing with at least some of the same incompatibility problems that Synopsys had encountered. Fortunately, it had amassed considerable experience in how IP blocks fit into the overall design flow and all the tools that process it, all the way from design capture to physical layout. Also, 3Soft brought almost 10 years of IP experience to the table and was already ISO 9000 certified, which offered some initial documentation and consistency guidelines. Finally, Mentor Consulting, Mentor Graphics' professional services division, had a strong track record of teaming with customers on SOC projects that included the design, integration and verification of IP blocks. These areas had become such a strong focus for Mentor Graphics Consulting that it created three Knowledge Centers to be centers of excellence in the disciplines of design reuse, SOC design and methodology, and system-to-silicon verification.

With the inception of Inventra, Mentor Graphics dedicated itself to a long-term strategy of providing its customers with IP blocks that were actual products, backed by a single, well-defined methodology for design reuse, as well as the tools to successfully integrate IP blocks into electronic systems. The vehicle for this strategy was the IP Factory, which developed a design reuse methodology and consistent set of deliverables that applied to all of Inventra's IP product offerings, whether developed internally or externally. At this point, it became apparent that much of Inventra's development work had applications that extended beyond the division itself and would be of mutual benefit to other EDA vendors and their customer base.

In developing the manual, both teams agreed on the key goals. With so many basic problems evident in both third-party IP blocks and internal IP development efforts, both companies clearly needed to establish a baseline of design practices that would produce usable IP blocks. Blazing new territory via radically new development methodology was clearly inappropriate.

The companies came to several conclusions. It was advisable to stick with fundamental issues. These included good planning, good specifications, careful and thorough design practices, good coding and thorough testing and complete documentation. In terms of design, it was important to emphasize simplicity, such as synchronous designs, good partitioning and careful time budgeting. The companies also developed guidelines for soft IP blocks (which can be modified by the user) and hard IP blocks (cores with a defined layout that cannot be altered by the designer). For soft IP blocks, it was important to develop designs that are easy to synthesize. For hard IP blocks, appropriate models for the end user had to be provided. The end result, the manual, was developed to help bring the development of IP blocks to a baseline of quality and usability that will encourage the widespread adoption of reuse as a basic design methodology.

The manual complements the efforts of the VSI alliance and will serve to accelerate the implementation of VSI standards through actual design for reuse. Rather than concentrating on development of integration specifications, the manual provides a methodology for creation of streamlined quality IP with the flexibility required to accommodate different platforms, design methodologies and system-verification environments. Only through the consistent use of proven IP blocks and design reuse practices will companies be able to take advantage of deep submicron technology and the astounding gate counts that it promises. Both Mentor Graphics and Synopsys will continue to update the manual with the latest findings in how to create and use IP blocks effectively as designer productivity continues to chase Moore's Law.