Examining the case for analog automation

Complete automation of the analog IC design flow is a concept that has been debated for decades. With total automation still a distant goal, the EDA community has focused on automating elements of the design process, such as placement, circuit optimization, routing and verification.

But why does 100 percent automation evade us still--and, indeed, should it even be the focus?

"It's a worthy goal, a bit like trying to put people on Mars: I don't know whether we'll ever get there, but a lot of good technology gets derived from that," said Randolph Fish, director of marketing, custom layout and routing at Cadence Design Systems Inc.

An op amp layout is automatically placed using Modgens and Analog Placer.

Designing chips on a lighted drafting table/font>

"I love tools and love to automate," said Chris Collins, Texas Instruments' analog EDA manager. "But I don't believe in analog synthesis, because analog isn't structured. There are behavioral languages and so forth, but you'll never have a usable form of analog synthesis, and I am not seeing a lot of effort put into this area by vendors anymore."

The skepticism about analog automation--or, more specifically, analog synthesis--is not that surprising when you consider that the annals of analog EDA history are littered with companies that tried to tackle the job and failed. Nowadays, EDA vendors talk more about productivity improvements than synthesis, and there has indeed been productivity success in the analog domain.

For example, demand from mid- to high-complexity analog and mixed-signal applications, where increases in transistor count and parasitics have driven up simulation time, has prompted companies such as Cadence and Gemini Design Automation to turn to multicore computing and multithreaded software techniques to improve simulation speed and accuracy.

But simulation is just one aspect of the analog design flow. One of the biggest bottlenecks is layout. "Many analog designers aren't able to get the whole chip together and start simulating until close to the time when the design must go out the door," said TI's Collins. "If there's a mistake, then it's back to layout."