Complete SoC Design, Verification Reign at DAC Exhibits

With the Design Automation Conference (DAC) upon us, EDA and silicon-IP vendors have made their annual big drive to present their latest and greatest products to the electronics community. Following the trend of recent years, most companies are releasing new products prior to, as opposed to at, DAC. This year, many of the more interesting chip-design-tool announcements fall into four areas:

• RTL design planning and virtual prototyping
• Design verification
• Design optimization
• Hardware/software co-design.

In addition to new and enhanced products addressing these topics, several companies have also made interesting announcements involving analog and mixed-signal (A/MS) design, hardware/software co-design, and high-accuracy extraction and analysis tools.

Atrenta has come out with a "predictive analysis" design tool, SpyGlass SoC, for dealing with the logic problems caused by integrating multiple silicon cores from several vendors onto a common chip. The tool lets designers create an RTL logical virtual prototype from which they can spot and correct problems that normally do not appear until later in the design flow, when they employ downstream synthesis, simulation, and physical-implementation tools. Typical logic-based multi-core problems include different clocking schemes for cores, non-compatible design-for-test (DFT) schemes, different reset techniques, and preferred design rules for the various downstream tools. Often, these problems will not be detected with physical virtual prototypes.

SpyGlass SoC uses a predictive analysis technique along with a fast-synthesis engine, logic evaluator, and testability technologies. Combining these, the tool ascertains a design's structure and function, and finds RTL-based problems not easily detectable by other verification methods such as rule checking, simulation, and formal verification. SpyGlass SoC addresses important SoC integration issues including clock phasing, synchronization, verification, reuse, and testability. For example, the tool identifies signal paths that cross clock domains and analyzes whether paths conform to selected synchronization rules. You can also detect problematic race conditions and combinatorial loops at the full-chip level prior to synthesis and simulation, and ensure that test mode controls, built into lower level blocks, are compatible. SpyGlass SoC identifies potential problems back in the Verilog or VHDL source code, aiding the designer in finding and correcting these problems. SpyGlass SoC is an extension of the company's SpyGlass software, a tool that checks RTL code in areas such as coding styles, RTL-handoff, design re-use, and clock/reset requirements.

While Atrenta addresses logic-design problems at the RTL level, Synopsys tackles the physical-design issue of timing closure, using the company's Physical Compiler in what the company calls an RTL Performance Prototyping (RPP) flow. Synopsys is targeting RPP to both soft silicon-IP providers and integrators (users), by enhancing Physical Compiler to allow it to perform RTL prototyping. You run the tool at the RT level to get a "pseudo-floorplan", which gives you a chip's aspect ratio, pin locations, macro (core) locations, and routing resource utilization. You then do static-timing analysis on this data to see if the chip meets timing specifications—Synopsys claims a close correlation between the pseudo-floorplan and a detailed floorplan that takes a lot longer to generate. Since it takes very little time to do a pseudo-floorplan, you can try different chip configurations and pin locations to find the one that has the best chance of meeting chip specifications while achieving complete placement and routing. Synopsys will have RTL Performance Prototyping available in an upcoming major release of Physical Compiler, Physical Compiler 2002.05.

Tera Systems is also announcing a new product, TeraForm-RTL Design Consultant (TeraForm-RDC), for spotting RTL problems prior to costly and time-consuming synthesis, simulation, and physical implementation. As is the case with Spyglass SoC and Physical Compiler, the designer at the RTL level using TeraForm-RDC does not have to be an expert in the physical implementation aspects of chip design to identify and eliminate certain down-stream design problems.

Using TeraForm-RDC, with its encapsulation of both expert RTL and physical-implementation knowledge and design practices, you can explore and debug a complete chip. The tool has a unique physical-modeling capability at RTL, allowing designers to investigate semantics, timing, area, congestion, synthesis constraints, and layout implementation-related issues, and then correct problems they may find. Along with standard rule checks, you can configure the tool to check for proprietary or vendor-specific errors and coding violations. Some of the checks TeraForm-RDC performs include identification of snaking timing paths, incomplete timing constraints, and congestion detection at the RT level.

The New Verdi software system from Novas Software takes a unique behavioral based approach to debugging digital chips. Verdi combines three technologies—behavior analysis, visualization capabilities, and symbolic design exploration—to help designers debug a chip at a behavioral rather than the traditional structural level. Novas designed Verdi to extend the capabilities in the company's well-known Debussy knowledge-based debug tool, making the new tool better suited for working with very complex or unfamiliar chip designs.

Verdi shares the same APIs as Debussy, allowing the debug tool to work with a broad range of logic simulators, formal verification and timing analysis tools, and other third-party applications. Going beyond Debussy's capabilities, Verdi adds formal mathematical analysis, temporal visualization, and symbolic exploration, letting designers analyze cause and effect relationships, visualize design behavior over time, and explore chip behavior with different bug fixes. Using synthesis technology, the tool automatically infers the logic functions of a design from the RTL description and then interprets simulation results to generate an internal model of actual design behavior over time, using register-flow and statement-flow graphs (Figure 1). You can also back-trace signals to show the behavior of unfamiliar designs. Using "evaluate" and "solve" operations, you can explore design behavior changes due to changes in register values or source code. Available for Verilog designs in July, Novas plans to add VHDL and mixed-HLD capabilities later this year.

Cadence Design Systems is adding Assertion-Based Verification (ABV) technology, supporting the Sugar 2.0 Accellera standard language, to its Verification Cockpit functional-verification tool package. ABV functionality includes Sugar 2.0 assertion language support, extended transaction-based analysis and debug, and new static-checking capabilities. The ABV capabilities let designers:

• Capture specifications, requirements, and assumptions as assertions
• Verify these assertions statically using static-check techniques, or dynamically using NC-Sim, Cadence's mixed-language simulator
• Detect internal errors at or near their source
• Record assertion activity as transactions in the same form as those already recorded from Cadence's TestBuilder, and Verilog and VHDL testbenches.

Cadence also announced SystemC open language support, available this fall, for design and verification in its NC-Sim and open-source TestBuilder products. Native support of SystemC in NC-Sim lets designers mix SystemC, RTL, and analog mixed-signal descriptions, which include Verilog, Verilog-A, VHDL and VHDL-A open languages. TestBuilder verification extensions to SystemC 2.0 let designers and verification engineers write reusable testbenches at a high level of abstraction in C/C++.

Addressing the problem of SoC physical verification along with RTL verification, Verplex Systems has enhanced two of its tools— the formal-verification Conformal Logic Equivalence Checker (LEC) and Transformal Logic Transistor eXtractor (LTX). Transformal accepts a switch-level Verilog or Spice transistor netlist as input and extracts a higher level Verilog description from the netlist. Both tools now perform verification on all logic blocks of complex SoCs from RTL to final layout-versus-schematic (LVS) netlist comparison. These blocks include memory, compiled datapath, memory control, silicon cores, complex I/O, and full-custom logic. The enhanced tools are particularly useful for verifying designs that have undergone layout changes and late timing optimizations to achieve design closure. Through tighter coupling to the transistor level, Conformal LVR lets designers compare final layouts to their RTL golden designs, helping detect design-implementation bugs.

Verplex will also add in Q3 a Conformal option to support complex arithmetic operators compiled from higher-level descriptions, often done in SOC design. These operators are difficult to verify using formal-verification technology due to the logical complexity of those circuits. Verplex uses proprietary adaptive algorithms that increase in efficiency as the comparison progresses to overcome this problem.

Combining simulation, acceleration, and emulation, Axis Systems has expanded its product line with the Xtreme-II verification platform. Xtreme-II features up to a large 100-million logic-gate capacity (in a twin-box configuration) coupled with more than 2 Gbytes of memory and a speed of 1 MHz. To aid in model reuse, the platform uses a technique Axis calls "abstraction binding". This technique lets designers reuse models at any level of abstraction—behavioral, RTL, gate, and discrete hardware model components—throughout the verification process, whether they are in simulation, acceleration, or emulation mode or any combination of modes.

The company's event-driven ReConfigurable Computing (RCC) technology enables capabilities such as VCD-on-Demand and hot swapping. VCD-on-Demand saves the simulation history for an entire design, eliminating the need to re-simulate when a bug is found, thus saving verification time. Hot swapping—switching from software simulation to accelerated simulation and emulation—lets you debug designs in a familiar software-debugging environment still using acceleration and emulation features. Although still a very expensive verification platform, pricing for an Xtreme-II systems starts as low as $.09/gate, making it a bargain compared to competing emulation systems.

Quickturn also has an upgraded version of one of their simulation/acceleration boxes. The Palladium verification system now has support for up to 128-million logic gates, 64 Gbytes of memory, and over 8000 physical I/Os for interfacing to the target system. Enhancements to Palladium include:

• A new high-speed channel between the workstation and Palladium, lowering inter-process latency and increasing performance over the previous channel.
• A tighter integration with Cadence's NC-Sim simulator and testbench automation tools, such as Cadence's TestBuilder and Verisity's Specman Elite, streamlining debugging at the transaction-level.
• A new IP-card form-factor interfacing silicon cores within Palladium to external target designs for both simulation/acceleration and in-circuit emulation.

You can buy or lease Palladium hardware and software, the latter through a Quickturn customer-access program.

Newcomer Zenasis hopes to make a big impact on static, cell-based chip design with its "hybrid optimization" technology. The new optimization technique, which works on a synthesized-gate netlist, operates at both transistor and cell levels. Upcoming tools from Zenasis will identify clusters of gates at a gate level of abstraction and map these clusters into new, design-specific cells that feature transistor-level optimization with fewer transistors and fewer interconnect wires (Figure 2). In the example of Figure 2, hybrid optimization reduced the gate-level cluster from five standard cells, 22 transistors, and nine wires to one cell with 13 transistors and six wires. This type of reduction also results in better speed, fewer logic levels, lower power and area, and reduced congestion for follow-on place-and-route tools. That's the good news—the bad news is that hybrid-optimization tools will not be available from Zenasis until early next year.

Monterey Design Systems' new version of Sonar combines fast physical prototyping with physical optimization capabilities. Enhanced tool features include detailed gate-level placement and increased speed—according to Monterey, Sonar can produce an accurate physical prototype in less than 4% of the amount of time it takes to fully place and route a large chip. Sonar can go from netlist to physical prototype on a five-million-gate design in less than five hours.

The tool's physical-synthesis engine includes logic re-structuring, technology mapping, cell sizing, buffer insertion, and post-placement optimization, outputting a ready-to-route physical implementation that includes fully implemented power and synthesized-clock networks. The new version of Sonar also includes the following: increased capacity, up to a five-million gate flat design; enhanced IR drop analysis for optimizing power networks; and the ability to use low-power cells whenever possible without sacrificing timing quality.

System-level EDA vendor CoWare has two new products for hardware/software design teams—the N2C System Designer and Advanced System Designer. System Designer helps system integrators, firmware developers, and verification engineers integrate hardware and software much earlier in the SoC design process. Advanced System Designer adds complex bus analysis and synthesis capabilities for enhanced interconnect automation and architectural exploration.

System Designer extends CoWare N2C's existing capabilities to provide C- or SystemC-based multi-processor hardware-software co-simulation. According to CoWare, you can get a speed improvement of between one and four orders of magnitude, compared with HDL-based hardware-software co-verification, using multiple levels of abstraction in C or SystemC. With System Designer, designers can mix untimed, timed-functional, and cycle-accurate behavioral abstractions with transactional, bus cycle-accurate, or pin-accurate communications abstractions.

System Designer also adds three new significant capabilities for the hardware designer, software developer, and system integrator.

• CoWare has optimized the co-simulation of SoC software with HDL-based hardware "out of the box", easing the adoption of a C or SystemC-based methodology by the hardware design team.
• There are new analysis tools for the software developer, including task-level Gantt, task-level CPU load, memory, and cache analysis tools. These tools provide a familiar environment for the software developer that eliminates the need to understand the HDL simulator or to debug hardware-dependent software using a waveform viewer.
• System Designer includes the ability to build, execute, and analyze software running on platforms, created using Advanced System Designer, which utilize complex multi-layer buses.

Advanced System Designer puts all of CoWare's implementation tools on top of System Designer, including new complex bus-analysis capabilities along with the company's recent second-generation Interface Synthesis. This combination of capabilities helps system architects find a bus architecture that gives the best tradeoff of high performance and low power for a particular application. Advanced System Designer let you model, synthesize, and evaluate different bus architectures quickly. Interface Synthesis technology automatically synthesizes the bus interconnect matrixes and crossbar switches, at the heart of multi-layer buses including ARM's AMBA 2.0 on-chip interconnect and STMicroelectronic's STBus. The tools also synthesize the necessary arbitration logic for multiple bus masters, along with all other bus logic, letting you validate an SoC platform architecture before proceeding to implementation.

LISATek is showing a new release of its tool suite—EDGE Processor Designer, RIM Software Designer, and HUB System Integrator—for designing embedded processors in a single, unified hardware/software environment. The company bases its design tools on LISA 2.0 (Language for Instruction Set Architecture), an extension to C/C++ (Figure 3).

You use EDGE to design all types of processors, including microcontrollers, DSPs, RISCs, and network processors. The EDGE tools let designers explore different processor configurations and instruction sets, helping them determine the best processor for a particular application. The new version of EDGE includes advanced memory simulation modeling capabilities, multi-processing tools, and bus-model generators. EDGE generates VHDL hardware representations of processors now, with LISATek promising Verilog and SystemC support later.

RIM generates a complete software development environment for the embedded processors that EDGE develops. The environment includes the company's Just-in-time Cache Compiler (JIT-CC), instruction-set simulator (ISS), code generation tools (assembler and linker), dis-assembler, and debugger. LISATek also plans a C compiler as a future option. New features in RIM include multi-loader support for common object-file format (COFF), executable and linking format (ELF), and IntelHEX, as well as user-defined formats, plus instruction history recording to assist in application debugging.

HUB lets hardware designers integrate and verify embedded processors generated by EDGE into an SoC environment. The new release of HUB includes a multiprocessor simulation capability to verify heterogeneous systems of embedded processors with a user-defined number of debuggers. The release also features a re-targetable simulation API for customization and interfacing with different SoC design environments, including Synopsys' CoCentric System Studio. The API lets a designer interface the embedded-processor's ISS model with third-party hardware simulators supporting Verilog, VHDL, and SystemC. The integration of the LISATek tools with CoCentric allows joint verification and analysis of algorithms, architecture, hardware, and software.

For RF chip and silicon core designers, Neolinear has announced a new multi-vendor design environment. The RF design flow includes integration of Neolinear's NeoCircuit-RF software for RF-circuit sizing and optimization with Agilent's Advanced Design System (ADS) and the Cadence RF/MS IC design flow. NeoCircuit-RF works with Agilent's ADS simulators, Cadence's Spectre RF simulator and the Cadence Analog Design Environment to automate the process of finding an optimized RF circuit. NeoCircuit-RF also captures design test benches, parameters, and goals for future design reuse. The tool uses a proprietary optimization engine that works with any topology, uses manufacturing variations, and does not require a partially sized starting point. Designers then simulate the optimized RF circuit with either ADS or Spectre RF.

Also for RF (and analog) designers, OEA International now has RF-PASS. The tool suite lets designers analyze interconnects and passive components on RF and analog chips. You can use RF-PASS to analyze complex multiple-layer interdigitated capacitors, inductors, transformers, resistors, pads, arbitrary interconnect, and any combination of these components. Using a GUI, you import layout data, define ports, select frequencies, and extract highly accurate frequency-dependent distributed Spice netlists with resistance, capacitance, inductance and mutual inductance. A bundled Spice-like solver processes the extracted-layout Spice representations and generates N-Port scattering, impedance, and admittance files (S, Y, and Z parameters). In addition, an optimization engine can automatically generate an equivalent lumped Spice model that fits the scattering parameters of the original extracted netlist—users can also provide their own custom template for fitting to equivalent lumped models.

RF-PASS includes high frequency effects such as skin effect in conductors and substrate losses through capacitive and inductive coupling. You can define multiple substrate layers to handle epitaxial wafers. The tool suite also allows multiple contacts to the substrate both on the top and bottom surface to properly model current flow in the substrate.

OEA has also upgraded HENRY, an inductance extraction tool for the calculation of package parasitic inductance, resistance, and mutual inductance. HENRY comprises three different solvers, covering a broad range of package structures. New tool features include frequency-dependent inductance and resistance, and a new graphical interface. Applications for the extractor include bond wires, package leads, and package ground-planes.

For RTL-to-gate-level synthesis, Synopsys has a new version of Design Compiler, the company's popular logic-synthesis tool. According to Synopsys, the new Design Compiler offers up to 2X faster run times, 15% higher circuit speed, and 14% smaller area than its predecessor. The new synthesizer also handles much larger designs, due to memory-usage improvements, including Interface Logic Models, 64-bit support, and other enhancements. Also added is a new easy-to-use compile command that results in an average of 11% faster designs, but represents a tradeoff of simplified logic-synthesis launching versus even more optimized design output.