First and foremost - how can a team of engineers verify the correct functional operation of every one of those billions of transistors in the presence of increasing pressure for shorter time to market? To further add to the challenge, another law has come into effect as well; the law of unintended consequences. As Moore's Law provided for exponential growth in transistors per chip, increasing power density followed as a direct result from doubling the number of devices switching at constantly higher frequencies. This situation becomes more critical when one considers that the largest market driver in the semiconductor industry is now consumer electronics, and the #1 application is cellular handsets that rely on battery operation. Design and process innovations have kept semiconductor technology advancing from one process node to the next, but now the dual challenge of completing functional verification along with verification of complex on-chip power management presents a major obstacle to further progress.

According to the 2006 International Technology Roadmap for Semiconductors Update on Design; many companies are addressing these issues by increasing the number of verification engineers to the point that they now exceed the number of design engineers by two to three times on many projects. The situation may be worse however, because surveys such as this may actually undercount the verification effort by focusing primarily on digital verification engineers, whose role in practicing formal methodologies such as VMM for SystemVerilog is well established and easily identified. Verification tasks performed by designers of analog, memory and custom circuits are not so easily measured.

The 2006 ITRS report also pointed out the growing need for verification of "non-digital effects". It is well known by now that analog/mixed-signal (AMS) content on SoCs has necessarily increased to provide the functionality required in consumer electronics. This in turn has created an increasing demand for AMS verification tools. Not so obvious is the fact that accurate analysis and verification of new generations of power-sensitive designs now requires the use of "non-digital" views of logic blocks and constantly increasing amounts of on-chip memory that can only be provided by AMS solutions. The migration of IC design to the 65nm and 45nm process nodes has increased the need for comprehensive transistor-level verification before tape-out. Verification engineers need not be concerned that their only answer to this problem is more SPICE simulation, which lacks the speed and capacity required for large 65nm circuits, since new solutions are available that deliver increased productivity and accurate, predictable results.

Verification Solutions Must Extend Beyond Digital Simulation
Functional verification of AMS designs is best performed by employing a hierarchical methodology that can directly consume digital and analog blocks in their native modeling languages. For RTL and gate-level blocks the preferred format is Verilog or VHDL, while analog blocks are modeled in SPICE format. A less robust alternative is to abstract analog behavior to a limited real-number model that a digital simulator can execute, and/or to create piece-wise linear switching models of digital circuitry that are compatible with SPICE. Either way, by attempting translation of functional models from one domain to another, the probability for error increases and verification coverage inevitably suffers.

Similar difficulties have detracted from the promise of AMS behavioral languages, such as Verilog-AMS. While mixed-signal behavioral models can be useful for architectural exploration, the lack of a robust means to synthesize AMS models that match true circuit behavior limits their use in verification. Modeling engineers can attempt to build more complex AMS behavioral models, by adding more circuit-like elements, but the end result is that they simulate as slowly as their SPICE counterparts. Time spent developing and testing a model does not payoff in a reduction of verification time. AMS extensions of HDL languages are more useful for constructing mixed-signal testbenches that combine the stimulus and procedural constructs necessary to simultaneously verify digital and analog functions and their interaction.

It is critical to verify the interaction between analog and digital blocks in a closed-loop methodology, a requirement that can only be met by a co-simulation solution that combines the best of both worlds; a fast RTL simulator for digital that is tightly coupled with a high-capacity Fast-SPICE simulator for analog. Interface elements are automatically generated to perform D-to-A and A-to-D conversion between domains. Such an approach can also utilize testbenches directly without translating vector sets. A direct-kernel integration of Fast-SPICE with HDL, such as provided by Synopsys' Nanosim and HSIM Fast-SPICE simulators integrated with Synopsys VCS, optimizes performance with the flexibility to instantiate mixed levels of SPICE and Verilog blocks throughout a design hierarchy. This solution retains the full set of features of the respective simulators; providing high-capacity Fast-SPICE transistor-level simulation along with high-performance Verilog or VHDL simulation that can be extended to include System Verilog. In some cases interoperability of a Fast-SPICE engine with an HDL simulator from a different vendor may be required. To address this need verification engineers can apply a co-simulation solution that supports the IEEE 1364 Verilog standard VPI interface (PLI 2.0), such as the Synopsys HSIM VPI co-simulation option that has been verified with HDL simulators from Cadence and Mentor.

Verification of On-Chip Power Management Is an AMS Problem
For several years, predictions have been made that the physical limits of semiconductor fabrication at the 65nm process node would result in devices where static leakage power would exceed a typical chip's dynamic operating power. The 2002 ITRS forecast projected a tenfold increase in standby power per device between the 130nm and 65nm process nodes (see Figure 1). More recently, these warnings appear to be validated as designers of 65nm chips have reported that managing leakage power has become their major concern. Fortunately, through a combination of process and design innovation, a meltdown due to too high on-chip power density has been avoided " at least for now. However, the introduction of new power management techniques leads to new requirements in verification before tapeout; including the need for comprehensive analysis to the transistor-level.

1. The 2002 ITRS forecast projected a tenfold increase in standby power per device between the 130nm and 65nm process nodes.

Leakage is, of course, an analog electrical effect. With millions of transistors on a chip, a conventional SPICE simulation methodology would be unacceptably slow and lacks the capacity for analyzing leakage effects for anything but a relatively small block within a 65nm chip. In order to control leakage, designers are employing power-gating with (multi-threshold) MT-CMOS transistors to power on and off large sections of a chip as needed. Higher-threshold devices are used to isolate more leaky blocks from the power supply rails during standby and power-down modes. Multiple power domains are also commonly used, to optimize power dissipation through the use of lower supplies where performance requirements are not effected. Level shifters, simple analog circuits, are then employed to translate logic signals between different power islands. Each of these techniques has introduced analog behavior that strains the capability of digital verification methodologies; but AMS verification solutions have been introduced to overcome these limitations.

A hierarchical Fast-SPICE engine, such as Synopsys' HSIM, is capable of providing the capacity necessary to perform simulation of power management circuits by partitioning a design across power domains, simulating only the active blocks as necessary. By coupling Fast-SPICE with an HDL simulator through co-simulation, higher simulation productivity can be achieved to verify power-down and power-on functionality. However, there are cases where the electrical effects of leakage in power-sensitive designs cannot reasonably be simulated through dynamic analysis, even with Fast-SPICE and co-simulation. When shutting down a block through an MT-CMOS power switch, designers must be wary that floating nodes are not propagated to CMOS inputs that could generate short circuits. Leakage is often the culprit here, because a floating CMOS input node will accumulate charge from device leakage currents and float to a voltage that can turn on a direct path from the power rail to ground. These problems will usually go undetected before they are seen in silicon, because the time constants of the voltage drift are too long to be seen, even in a dynamic Fast-SPICE simulation, and a digital verification methodology misses the effect altogether.

The answer is to perform static, vectorless transistor-level analysis of power-management circuitry with a tool that can propagate logic states to trace leakage paths, while using SPICE models to measure currents, and automatically identify any floating nodes that are in danger of causing short-circuits (see Figure 2). Synopsys' HSIM^plus CircuitCheck^TM is able to provide this solution by virtue of its integration with a high-capacity hierarchical simulation database and Fast-SPICE engine. Standalone circuit checking programs can't handle large circuits, and are limited to performing only simple topology checks of connectivity errors and electrical rules, since they lack a SPICE analysis engine and any awareness of high or low impedance. CircuitCheck performs vectorless analysis with the same SPICE models, connectivity of devices and power rails that are used for dynamic simulation, avoiding wasted time spent on a lengthy transient analysis to detect potentially destructive leakage paths. Through vectorless leakage analysis, coverage is increased to detect problems before they reach silicon.

2. SPICE models measure currents and identify any floating nodes that may cause short-circuits.

Non-Digital Effects
IR Drop Is A "Non-Digital" Effect
At 65nm, designers have no choice but to perform verification of power-management and leakage control circuits in the context of accurately modeled supply rails. Perhaps the most significant "non-digital" effect is the dynamic IR drop that renders supply rails as constantly varying analog circuits, to the point that a digital model with fixed logic levels and slew rates is no longer valid. The days of assuming ideal, fixed voltage supplies have long passed. With minimum supplies down to one volt at 65nm, there is no spare headroom left for meeting performance specifications. Surges in supply current as blocks are powered on and off can temporarily starve blocks further down the rail from the source. Timing shifts are the result, which can wreak havoc in a digital verification methodology that fails to take dynamic IR drop into account. Designers who rely on de-coupling of timing and power rail analysis, as is quite common when verification tools lack the capacity and tight integration to handle both, risk the possibility of timing failures by not accurately accounting for the true impact of IR drop (see Figure 3). To compensate, designers will often over-design the power rails, leading to a costly waste of very expensive silicon. AMS solutions are required in order to accurately analyze the power rails with parasitic effects, while directly coupling dynamic currents that are measured to the transistor-level, so that IR drop and its effect on timing can be observed simultaneously.

3. Designers must accurately account for IR drops.

For complete analysis of IR drop on an SoC a hierarchical, multi-step approach provides the highest measure of verification coverage and productivity. The first step, to detect gross errors in power bus routing, is to apply a static analysis tool which measures the extracted power and ground nets directly from the post-layout parasitic file. Synopsys' HSIM^plus SPRES option provides such a capability, by performing complex measurements of mesh resistance on power and ground nets, analyzing the paths from power pads to each block's power nodes. Internal power nets can be analyzed as well. This approach yields the quickest turn-around-time (TAT) for repair of the power bus, before time is invested in a more extensive dynamic analysis. A static power net resistance tool integrated with a Fast-SPICE circuit analysis engine can fully analyze a power/ground net in minutes.

After a static screening of the power nets is completed, a direct-coupled dynamic analysis will provide the most accurate view of timing and other performance parameters as they are impacted by IR drop. This is especially crucial for analog, mixed-signal circuits, and memories but can affect digital circuitry as well. Many so-called "dynamic" IR drop solutions de-couple the measurement of switching currents from the calculation of IR drop. By measuring device switching currents without having the power net parasitic resistance back-annotated into the circuit, capacity and performance of the analysis may be improved but the currents that are measured are not accurate. A de-coupled IR drop methodology performs dynamic analysis with an ideal power net; totally omitting the timing impact of IR drop and resulting in over-estimation of peak switching currents.

High capacity for post-layout simulation is required to perform a direct-coupled analysis of IR drop on a 65nm design. Coupling effects in large, flat post-layout parasitic netlists can destroy the advantage of a Fast-SPICE engine if hierarchical partitioning cannot be maintained. Synopsys' HSIM^plus PWRA power net reliability analysis solution, along with HSIM^plus PLX post-layout acceleration, provide a solution based on direct-coupled analysis for simultaneous verification of timing, IR drop, and electro-migration effects " which is critical for ensuring reliability of 65nm wiring. Integration with Synopsys' PrimeRail tool provides a complete Systems on a Chip (SoC) solution encompassing custom designs at the transistor-level up through the gate and RTL levels for ASIC flows.

Summary
With management of power becoming the top design challenge at 65nm, verification methodologies must adapt to include coverage of non-digital effects such as leakage power, detection of floating nodes, and the impact of dynamic power supply rails on device performance. In order to achieve complete verification coverage there is an increased need for comprehensive transistor-level analysis before tape-out. Traditional SPICE and most Fast-SPICE tools are inadequately equipped to provide the capacity, performance and level of analysis required. For designers and verification engineers, new solutions such as vectorless circuit checking tools, static power net resistance analysis, and direct-coupled dynamic IR drop simulation are available to address the challenges of 65nm power-sensitive designs.

About the Author:

Mike Demler is the HSIM^plus Product Marketing Manager at Synopsys. He is the author of the book High Speed Analog-to-Digital Conversion, published by Academic Press.