Analog/RF Design at Silicon Laboratories
Silicon Laboratories offers a diverse portfolio of high-performance, analog-intensive, mixed-signal ICs that provide significant advantages in performance, size and power consumption. These patented solutions serve a broad set of markets and applications including consumer, communications, computing, industrial and automotive. These designs are typically analog- and/or RF-intensive, using a variety of complex blocks that include sigma-delta ADCs, PLLs (frac-N and integer-N), DLLs, dc-dc converters, PHYs, CDRs, frequency synthesizers, transmit chains and receive chains. These types of design blocks represent some of the biggest challenges in our design flow is verification and characterization.

Characterizing Complex Analog/RF Blocks
Over the years, we established a proven and robust transistor-level SPICE-based flow that works well for small analog and RF blocks. Our flow minimizes post-tapeout issues, and it is a requirement for our designers. Our block-level verification needs are not unique: we require pre-layout and post-layout circuit simulation, validate process corners, run noise characterization and perform RF analysis on periodic circuits. We depend on the "golden" SPICE accuracy with tight tolerances to validate functionality and performance. Without this accuracy, we would face a significant risk of taping out an analog or RF block that is not functional or does not meet specifications.

One of our key challenges was to scale our SPICE-based analog/RF verification flow as the complexity of our analog and RF blocks increased. Our design complexity is growing at a very rapid pace, driven by both the integration of analog functionality into SoCs and the growth in new functionality requirements in the markets we serve. The SPICE flow we use for small blocks was insufficient for our complex analog/RF circuits. Simulating these blocks required days to weeks, and in many cases, would not converge at all.

We also need to verify our analog/RF ICs at the top-level. This helps us ensure that we have correct full-circuit connectivity, functionality and performance specifications. Finally, we want to extend our methodology to support a mixed-signal flow with fast gate-level and behavioral Verilog-based simulations for the digital portion and SPICE-accurate transistor-level simulation for the complex analog/RF blocks. Again, traditional SPICE runtime and convergence issues limited us in pursuing this flow.

Digital FastSPICE Tools Fall Short
One of the alternatives we tried for our complex analog/RF block verification is FastSPICE tools, originally developed for digital and memory circuits. These tools are faster than traditional SPICE but at the expense of accuracy. They use simplified device models, partition the circuit into independent sub-circuits, require block-level simulator tuning and rely on hierarchical modeling. We found that these simplifications sacrifice accuracy to a degree that they were impractical for our leading-edge analog/RF circuits. The problems we encountered included having to tune the simulator extensively block-by-block, inability to get DC convergence and results that missed the targets we measured in silicon.

Our Experience with Analog FastSPICE
We had a breakthrough when we started using Analog FastSPICE. AFS produces results that are identical to our "golden" SPICE tool down to the SPICE noise floor, at least 5x faster and with much higher capacity. AFS finishes week-long SPICE simulations in only days and day-long SPICE runs in only a few hours. This performance and capacity allows us to simulate large circuits and verify our circuits at the top-level as well.

It was important that AFS did not cut corners and had the same capabilities as our traditional SPICE tool. A true test for the overall functionality of the tool is observing its behavior on highly non-linear circuits, since circuit simulators typically have difficulty handling non-linear behavior. One of the best ways to do this is to perform a transient simulation of a real-time clock (RTC) circuit to test RTC current consumption with complex digital control sequence. Figure 1 shows the results of AFS simulation of a RTC circuit. The RTC current measurement shows many sharp current pulses over long simulation time. The result is extremely accurate and predicts a leakage current that matches silicon.

1. Analog FastSPICE Transient Results for RTC.
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AFS plugs directly in our existing flow using the same netlists, models and testbenches. The output format is the same as our SPICE simulator, so we can process it with our existing post-processing scripts.

Analog FastSPICE Results
This section provides results of the simulation of three complex analog/RF blocks using our traditional SPICE tool, a digital fastSPICE tool, and Berkeley Design Automation Analog FastSPICE. Table 1 summarizes the results.

The first circuit is an automatic gain control block (AGC) with bandgap and bias circuitry. It also contained several Verilog-A models. We ran a transient simulation to verify the ramp-up to the DC operating point. Our traditional SPICE simulator took 13.5 hours to complete. The digital fastSPICE simulator struggled and could not successfully run this circuit. AFS finished the simulation in 22 minutes with identical waveforms for a 36x speed-up versus SPICE.

The second circuit is a third-order sigma-delta ADC with 9-bit resolution. It has a 1 MHz bandwidth, a 16 MHz sampling frequency and a 1V 200 KHz input. We had two versions of this circuit: a pre-layout version with 14,882 elements (11,265 MOS) and a post-layout version with 63,642 elements (14,832 MOS). We ran transient simulation the pre-layout version for 63 us and then post-processed the data to calculate the signal-to-noise ratio (SNR). The traditional SPICE simulator, the digital fastSPICE simulator with very tight settings, and AFS predicted similar SNR results. AFS complete the run 27 times faster than traditional SPICE and more than four times faster than digital fastSPICE. Figure 2 shows the AFS results for the sigma-delta ADC noise profile. The top red curve is the ideal response and the bottom blue curve is the result with parasitic extraction. Given the AFS performance advantage, it was the only tool we used on post-layout circuit.

2. Analog FastSPICE Noise Profile for Sigma-Delta ADC.
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The third example is a PLL with 3 GHz VCO frequency, 24 MHz reference frequency, and 150 KHz bandwidth. We ran a 20us transient simulation with traditional SPICE to measure the locking process. For traditional SPICE, we had to break the run into two stages: the first stage used liberal accuracy in order to quickly get near the locking state, and the second stage used the result from the first stage as initial conditions and switched back to moderate for more accurate locking results. The whole process in traditional SPICE took up to three weeks. Digital fastSPICE required tuning block-level accuracy settings and then took 40 hours. AFS completed a 25 us run in 20 hours. AFS was 25 times faster than traditional SPICE. Compared to digital fastSPICE, AFS did not require any tuning, ran two times faster and produced SPICE-accurate results.

We use our simulation results to make decisions that have a huge impact on our company. It is extremely inefficient to respin designs because complex analog/RF blocks are not meeting functional or performance specifications. The performance improvements of the digital fastSPICE tools relative to the traditional SPICE simulator come with a significant cost. The accuracy of the digital fastSPICE tool is never guaranteed to be the same as that of traditional SPICE. Traditional SPICE always runs with tight accuracy as controlled by the simulation relative tolerance (reltol), which affects size of time-step and controls the allowed difference between iterations before converging at a timepoint and moving on to the next. SPICE defaults reltol to 1e-3 (0.1 percent) with typical values set from 1e-2 to 1e-6. We compared AFS simulation results against those of traditional SPICE simulation with different reltol settings. Only after we are sure that a tool delivers the required accuracy do we start to look at the performance and capacity capabilities.

We found that Analog FastSPICE has the required accuracy and in several cases is more than 20 times faster than traditional SPICE. Now, what is truly incredible is that in our circuits, AFS was also be two to four times faster than the digital fastSPICE tools without using techniques that can compromise accuracy. Essentially, we get the accuracy of traditional SPICE with better performance than digital fastSPICE.

Summary and Future Work
Analog FastSPICE is the best simulator we found in terms of accuracy, speed, capacity and ease-of-use. It delivers true SPICE accuracy with higher performance than the existing digital fastSPICE tools for our applications. AFS is ideal for large transistor-level simulation " including analog behavioral models " and does not require block-level tuning. In our experience, its performance is five to 30 times that of other SPICE simulators and can converge on circuits much larger than traditional SPICE tools can handle.

For future work, we are looking at using Analog FastSPICE noise analysis, including random device noise analysis of non-periodic blocks such as sigma-delta ADCs and fractional-N PLLs. We are also looking forward to using Analog FastSPICE Verilog-D co-simulation in the future. This capability would enable us to extend our methodology to tackle much larger mixed-signal circuits, with Verilog simulation for digital blocks and AFS transistor-level simulation for the complex analog/RF blocks.

About the Author
Yiqun Lin is Staff CAD Engineer at Silicon Laboratories Inc. He has more than 15 years combined EDA and design experience. He has engineering degrees from Florida Institute of Technology and Shanghai Jiao Tong University with 3 IEEE publications and holds 2 US patents.