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Design Article

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1/22/2013 2:27 PM EST

This is a late reply of course.

The circuit which appears to be ...

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patrick.mannion

5/26/2011 7:46 PM EDT

Hi Chaz, thanks for the question. It's one of our older Design Ideas so we'll ...

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# Op amp linearizes response of FET VCA

## 9/5/2002 3:00 AM EDT

FETs find common use in VCAs (voltage-controlled amplifiers) and attenuators, in which the FET serves as a variable resistance. A control voltage applied to the gate sets the channel resistance and overall circuit gain. You frequently need to select individual FETs because of wide spreads in FET characteristics. The circuit in Figure 1 uses a master-slave servo technique with a matched-FET pair to implement voltage-controlled variable gain. This gain is a linear function of the applied control voltage, VC. In contrast with variable-gain circuits using a single FET as the gain-control element, the circuit in Figure 1 exhibits minimum gain for VC=0V and features a linear increase in gain with increasing VC. The self-biasing operation of the circuit also compensates for unit-to-unit variations in the FET characteristics, thereby making device selection less critical.

The circuit maintains the drain voltage, VDS, of Q1A at a low value (VREF=50 mV) to ensure that the FET operates in the resistive region of its ID versus VDS characteristic curve. Op amp IC1A servos the VGS of Q1A to maintain VDS at VREF, while Q1A sinks the current from the Howland current source IC1B. The sourced current is ID(mA) =VC/R5(kΩ), where VC is the control voltage. The channel resistance, RD, in kilohms is then RD=VREF/ID=0.05/ID=0.05×R5/VC. The same VGS applies to Q1B through R12. Because Q1 is a well-matched monolithic dual FET, Q1A and Q1B have identical channel resistance, RD. VGS varies from approximately 370 mV (which D1 limits to prevent gate-source conduction) to VP (approximately –1.7V for the 2N3958) as VC varies from 0 to 5V. IC2 is a variable-gain, noninverting amplifier, in which the controlled RD of Q1B sets the gain: Gain=1+R9/RD=1+R9/(VREF×R5/VC).

The maximum gain is 1+R9/R0. R0 is the minimum channel resistance for VGS=0V, approximately 450Ω for the 2N3958. The minimum gain is unity, when the FET does not conduct (VGS=VPINCHOFF). The circuit attenuates the audio-input signal level to lower than 10 mV p-p. This attenuation minimizes distortion in the FET and also sets the clipping level at the output of IC2. R13 and C5, in combination with R12, reduce distortion at higher signal levels. With the values shown, the gain increases linearly from –55 to 0 dB as VC varies from 0 to 5V. The circuit accepts a 6V p-p input signal. Figure 2 shows the result of modulating a 500-Hz sine wave with a 0 to 4V triangle wave.

For best performance, IC1 should be a low-offset, low-input-current unit, such as the OP-290. IC2 should be a high-gain-bandwidth-product, low-noise amplifier, such as the NE5534. You can successfully use inexpensive units, such as the LF353 and LF351, at reduced gains. You can also operate the circuit from ±5V supplies (with R1 changed to 100 kΩ), using an OP-290 for IC1 and a TL031 for IC2. The maximum supply current for ±5V operation is 0.33 mA, showing that low-power operation is possible.

Is this the best Design Idea in this issue? Select at www.edn.com.

anonymous user

5/26/2011 2:30 PM EDT

I don't quite get the purpose of the opamp that goes know where? how is this creating some kind of effect on the input when its output is left open? i get it may effect impedance but a whole op amp circuit for that?
i have never seen this before.....Enlighten me...

1/22/2013 2:27 PM EST

This is a late reply of course.

The circuit which appears to be floating generates a negative resistance.
I have no idea why it is there.

David.

patrick.mannion

5/26/2011 7:46 PM EDT

Hi Chaz, thanks for the question. It's one of our older Design Ideas so we'll need to track down the originating author. Stay tuned. We'll get back to you as soon as possible. Best regards,