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Circuit secures bootstrap operation under light load
Chee H How, Kuala Lumpur, Malaysia; Edited by Martin Rowe and Fran Granville
5/12/2011 1:00 PM EDT
A previous Design Idea highlights
a potential issue of a bootstrap
IC under light-load or prechargedload
operation (Reference 1). The
circuit in Figure 1, with the additional
circuit in the green box, fixes the problem
of a voltage dip in the bus-voltage
signal. The waveforms in Figure 2 demonstrate
how this problem takes place
in buck converter IC1B when its output
voltage, VBUS, dips below the regulation
point at a fixed rate under no load. By
inspecting the other traces in Figure 2,
you can conclude that the dip of VBUS
occurs when the bootstrap voltage falls
below its threshold of 8.66V (Trace 3),
causing the buck converter’s switching
action to cease. This situation intensifies
when the bus voltage approaches
the input voltage.| Read More Design Ideas |
During freewheeling operation of
DCM (discontinuous-conduction
mode), the output signal (Figure 3,
Trace 4) tends to settle at the bus voltage
after inductor L1 completely discharges.
This action prevents bootstrap capacitor CBS from charging, which
eventually causes the bootstrap voltage
in Figure 2 to fall below 8.66V. Hence,
the buck converter stops switching.
The circuit in Figure 1’s green box
aims to solve the problem. It starts by
tapping the input signal to the bootstrap’s
high-side driver to generate an
inverted and delayed short pulse to
control Q2. Upon activation, Q2 forces
the output signal momentarily low,
which provides an opportunity for CBS
to charge. R8, R9, R10, R11, and C9 set
the turn-on period of Q2. This period
must not exceed the dead time of the
PWM (pulse-width-modulated) signal.
If Q2’s turn-on time is too long, the
converter’s efficiency will degrade, or
the CBS might not sufficiently charge.
Inadequate charging of Q2 involves
multiple component values and operating
parameters, such as Q2’s turn-on
time, and you might have to empirically
tune the delay time to accommodate
for these effects. The values in
Figure 1 produce a Q2-turn-on time of
1 μsec and delay time of 450 nsec in a
70-kHz switching frequency.
The Q5 network is optional. It lets
you disable operation of Q2 when it is
not necessary by linking the P_on/off
signal to an open collector, Q6. The
low section of IC1A drives Q2. You
must experimentally select the value
of R6. A resistance value that is too
low induces larger current spikes upon
activation of Q2. On the other hand,
a resistance value that is too high
causes CBS to insufficiently charge.Resistor R7 and capacitor C8 control the delay time between the falling edge of the input signal to the bootstrap’s high-side driver and the rising edge of IC1A’s LVG (low-voltage) pulse. Figure 4 displays the waveform of the same converter after the inclusion of the additional circuit. In this case, VBUS (Trace 1) remains stable and the output signal from the buck regulator switches continuously, lacking the gaps with switching that the waveforms of Figure 2 show.
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