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Design Article

Analog: back to the future, part one

Steve Taranovich

6/5/2012 1:56 PM EDT

Kludge boxes
According to Maida, the company also used color keys to compare one layer with another (Figure 2). The color keys were printed on Mylar sheets representing one of the physical layers, and each layer was assigned a color, such as red for the base or green for the collector. When the designers stacked the two colors over a light source, they produced a third color. This approach provided an efficient way to check whether a part of the geometry was missing or incorrectly drawn. The designers also developed so-called kludge boxes to verify the performance of the design and sometimes for use in production-test equipment (Figure 3).

“Kludge boxes were a necessity in that test equipment did not exist that could measure the performance of the IC,” says Moraveji. “These boxes often used some clever measurement tricks, which would also find their way into the data sheet.” According to Moraveji, the designers used transistor-kit parts in breadboarding a new design idea or to prototype a chip. They performed comprehensive measurements on a breadboard to ensure the validity of a design idea. “Breadboarding was fun, as well as challenging,” he says. “During the process, if a component went bad, it was extremely painful to debug and get it to work again. Technicians, who used to do a neat breadboard, were valuable parts of our team in the development phase.”



Designers used to be able to get into the transistor-level details and even modify the transistor design to create ICs. Today’s designers instead receive standard cells with which to design; they cannot modify them because manufacturing does not support modified designs. In the early days, time to market was less critical than it is now. A 50-transistor circuit—including breadboard design; layout; debugging, which often took place on a probe station; and, typically, some mask changes—would take 18 to 24 months to complete. Now, a period of eight to 10 months is the norm for several-thousand-transistor designs (Figure 4).


Click image to enlarge

The designers used simulation tools for validation but first had to perform manual calculations, and developing breadboards was a standard practice until the mid-’80s. Sometimes, they had to use slide rules to make the paper design work before building the breadboard. They also couldn’t use many library textbooks because they were developing new designs, especially in CMOS. According to Archer, researching articles in various IEEE journals was often more insightful and useful than using textbooks. And, according to Monticelli, recent engineering-school graduates would try to find a good mentor who used blackboards because there were no whiteboards in those days. You learned by reading the latest published papers and meeting other engineers at the watering holes in Silicon Valley. “In many cases, we had to take a multitude of measurements and then use the data to create an explanation [about] the operation of the circuit,” says Dietz.

Moving to plastic-mold compounds caused stress effects that changed low-offset voltages in a chip after the application of the mold. “Sometimes, we would not offer the premium A-grade specs in the plastic package,” explains Maida. “The same part often had two or three electrical grades and two or three temperature grades: commercial, industrial, and military.” He adds that designers always tested military-temperature-range parts over temperature but almost never tested commercial parts in the same way.

According to Dietz, the op amp served as the canary in the coal mine for uncovering any process problems. The sensitive nature of the tight specs in an analog IC provided warnings when the process started going awry. Designers back then had never heard of the phrase “guaranteed by design.” Instead, they “tested the daylights” out of the IC during development. However, Maida claims that this testing was not true for production testing. “Good managers knew what could be put in as a design limit,” he says. “The test-everything mentality came in later, toward the late ’80s, as [part-per-million] quality levels became important.” However, Maida adds, they had to characterize the parts on the bench, which always involved manual measurements and, sometimes, kludge boxes for the tricky measurements, such as settling time, sample-and-hold acquisition time, and linearity.

Fast-forward 40 years, and the customer has hundreds if not thousands of op amps and multiple suppliers to choose from, says Dietz. Once engineers get comfortable with an op amp, they tend to use it over and over again. If they need a little better performance, then the chances are that they can find a product that fits the bill. “It is rare that someone comes to us today and asks for a new op amp,” he says.




Guru of Grounding

6/7/2012 4:29 PM EDT

Great piece! In looking at Fig 5, there seems to be an error ... shouldn't the other emitter of the double-emitter transistor (resolution too poor to read its designator) connect to the emitter of Q2 rather than Q4? I loved the LM318 for wideband analog work and designed them into lots of gear!

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Sergio_B_Franco

6/7/2012 4:46 PM EDT

Yes indeed, there is an error. One can confirm by looking at the "old" LM318 datasheets, which you can easily download from a number of manufacturers.

Analog cheers, sf

http://online.sfsu.edu/~sfranco/

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transistor_guy

6/7/2012 9:12 PM EDT

Yes, the posted schematic does indeed have the 2 errors mentioned above: the incorrect connection of Q5 upper emitter and missing dot for Q6 collector connection. You guys passed the test!

Inverse-mode transistor Q6 is a clever way to improve slew rate of the emitters of Q1 and Q2. Junction isolated transistors have significant collector-to-substrate capacitance (Cjs) especially on these older processes. Using the inverse-mode transistor, there is no large epi-substrate junction capacitance to degrade the falling slew rate at these nodes. Also, adding an extra emitter takes up less space than the additional transistor which would have been required if these currents were to be produced using forward-active NPNs. In those days we cared about such things (which we measured in square mils!)

Mike Maida
Distinguished Member of Technical Staff
Texas Instruments
(formerly with National Semiconductor)

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transistor_guy

6/7/2012 9:14 PM EDT

I have said "inverse-mode transistor Q5!"

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steve.taranovich

6/8/2012 12:54 PM EDT

That’s why I love EDN’s technical audience! I have to commend you guys and gals for not just reading or perusing an article, but examining it in detail to understand it and comment on anything that seems awry.

Kudos to you “Guru of Grounding” and “Sergio B Franco” for pointing out a not so obvious error in Fig. 5 schematic! You guys get a “beer check” beer from me if you come to DESIGNEast, DesignCon or DESIGNWest.

Now here is what happened: We re-draw a schematic that is not legible enough for our readers to examine. In this special case, I have the old, original schematic images and I wanted to keep those in the article as is, not for accuracy of the design necessarily, but just to show the relative simplicity of the architecture as compared with today’s designs. You can even click on these images and see an enlarged version.

Well---“mea culpa”---my error, I asked that Figures 1 and 4 be kept as is (and they are the originals) but I overlooked Fig. 5 and it was re-drawn---with an error! Sorry, but you guys and gals that are our audience are the best! I love it!

Best regards,
Steve Taranovich

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Sergio_B_Franco

6/7/2012 4:59 PM EDT

The double-emitter transistor is Q5, biased in the reverse-active region to provide a low emitter current bias for the Q1/Q2 pair. Come to think, there is yet another error: a missing dot at the point where Q6's collector joins R5, R6, and R7. Ah well...

sf

http://online.sfsu.edu/~sfranco/

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Tucson_Mike

6/8/2012 5:01 PM EDT

Great article Steve, nice to see all these luminaries quoted.
You do make a side comment about device sized and features being delivered in discrete steps for modern processes - I am by no means an IC design level expert but I believe some advanced bipolar processes include P-cells (parameterized cells) to allow completely customized active devices at any place in the circuit with all the EDA layers set up to handle that (the tough part is parameterizing all the model features for simulation).
Also, the layout parasitic extraction has come a long way but I still sit in meetings where not extracting the metal run resistance (LPR) bites us in the posterior. Still work to do there apparently.

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steve.taranovich

6/8/2012 8:27 PM EDT

Hi Tucson Mike,
Thanks for the added insight regarding P-cells and layout parasitic extraction considerations

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DaveMcGuire

6/13/2012 9:38 AM EDT

Thank you for this great article! I believe it's important to understand where what we have today came from, so we can better guide where it's going. I hope to see more articles like this in EDN in the future.

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izadinia

8/7/2012 11:56 AM EDT

This is a great article. It brings back a lot of memories. The first time I used the INLIC kit parts, I used the split collector Quad PNP (A43 in diagram). I left one of the collectors open since the circuit did not need the fourth collector. I soon learned about saturating PNP's and how none of my bias currents worked. This is the times, when you could actually learn circuit design on the bench by making mistakes on real circuits. Learning the hard way, you will never forget!
Thank You for the great article.
Mansour Izadinia

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ZekeR

2/18/2013 2:56 PM EST

More missing dots at Q2's collector and Q32's emitter...

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