Design Article
Comment
Juan Medrano
This is worth reading one time and another. For a beginner like me, I just feel ...
MSimon
I always use "too many" bypass capacitors in prototypes. It saves trouble. If ...
Successful PCB grounding with mixed-signal chips - Part 1: Principles of current flow
Mark Fortunato
8/27/2012 10:05 AM EDT
Board-level designers often have concerns about the proper way to handle grounding for integrated circuits (ICs) which have separate analog and digital grounds. Should the two be completely separate and never touch? Should they connect at a single point with cuts in the ground plane to enforce this single point or "Mecca" ground? How can a Mecca ground be implemented when there are several ICs that call for analog and digital grounds?
This series of three articles comprises a basic tutorial on proper printed circuit board (PCB) grounding for mixed-signal designs. For most applications a simple method without cuts in the ground plane allows for successful PCB layouts with this kind of IC. Below we will learn about this method and that the basic principles used here can be extended to handle more complex and difficult applications.
We begin this Part 1 of the article with the basics: where the current flows. In Part 2 we will learn how to place components and route signal traces to minimize problems with crosstalk. In Part 3 we move on to consider power supply-currents and end by discussing how to extend what we have learned to circuits with multiple mixed-signal ICs.
Follow the CurrentRemember that we call a collection of connected electrical or electronic components a "circuit" because currents always flow from a source to a load and then back via a return path—a circle of sorts. Keeping in mind where the current flows, both in the direction intended to do the desired job as well as the resultant return current, is fundamental to making any analog circuit work well.
And, yes, all digital circuits are analog circuits; they are a subset for which we assign meaning to only two states. The transistors and other components, as well as the currents and voltages within the circuit, still operate by the same physical principles as other analog circuits. They will induce return currents in the same way as any other circuit.

Figure 1 illustrates the simplest of connections in a design: a direct connection from one chip to another. Taken as an ideal circuit in an ideal world,1 the output impedance of IC1 would be zero and the input impedance of IC2 would be infinite. Therefore, there would be no current flowing. In the real world, however, current will flow from IC1 and into IC2, or the reverse. What happens to this current? Does it just fill up IC2 or IC1? That is a facetious rhetorical question.
Actually, there must be another connection between IC1 and IC2 to allow the current flowing into IC2 from IC1 to return to IC1 and vice-versa. This connection is usually ground and is often not indicated in a digital section of a schematic (Figure 1). It is at most implied by use of ground symbols as shown in Figure 2a. Figure 2B shows the full circuit for current flow.

Of course, the ICs themselves are not the sources of current. The power supply for the circuit is. To keep things simple, we assume a single power rail and think of the supply as a battery. To be complete, we bypass the supplies to ICs with capacitors.
All DC currents ultimately start and end at the power source. Figure 3 shows the complete circuit with DC current flow when IC1 is sourcing the current indicated.

For high-frequency signals ("high" largely determined by the bypass capacitance and power-source impedance) the current starts and ends with the bypass capacitor. Figure 4 shows the high-frequency signal current flow.

It is important to remember that an output is not always the source of currents. For example, consider the case where an output from IC1 is connected to an input of IC2 which has a pullup resistor to VDD. Figure 5 shows transient (high frequency) current flow for this situation with the current coming from C2 through the pullup in IC2 over to the low-side FET in IC1, which is on, and then through the ground lead of IC1 to the ground lead of C2. While IC1 is the "driving" device, sinking current at its output pin by shorting it to ground with a FET, the current source is from C2 through IC2.

If the output pin of IC1 in Figure 5 stays low for a long time, then the static current that will be drawn will come directly from the power source (Figure 6).



Kyle B
8/28/2012 10:00 AM EDT
Thank you Mark for one of the best explainations of this phenomenom that I've seen yet! I've seen this written many different ways, this paper is definitely a "keeper". I'll be using it to help train the "newbies" as we hire 'em :)
Looking forward to part II !!!!
Sign in to Reply
Mark Fortunato
8/28/2012 7:29 PM EDT
Kyle, thanks for the kind words. I developed this appoach over the years of explaining it to customers and helping them make their designs work with our chips. Having to go over the same concepts many, many times helps to clarify one's understanding. Keep teaching those newbies and you will find yourself better understaning the stuff you are teaching.
Sign in to Reply
MSimon
12/21/2012 6:53 AM EST
I always use "too many" bypass capacitors in prototypes. It saves trouble. If the design goes into production I like to see how much that can be reduced before trouble. It gives some idea about how much costs can be reduced. In the TTL wire wrap days with boards that were mostly power, ground, and sockets - one bypass capacitor (.1uF) every other chip was considered adequate. I would make that one every chip these days. Plus I add a 4.7uF (at low voltages) at every chip just to be sure. Backing off the on 4.7s for production.
BTW high speed digital is sometime prone to transmission line effects at distances as short as one inch. Depends on if you got a "good" (very fast) set of production chips. Note: delays on some of the faster chips are quoted as fast as .5nS. The edge speed goes up accordingly. It is the speed of the edge that matters. Termination (or capacitive loading at the source) can tame this. If you don't need speed don't use it.
Sign in to Reply
CCarpenter
8/28/2012 2:07 PM EDT
I too look forward to the next installment. I think this series is going to be very helpful.
Sign in to Reply
mtripoli
8/30/2012 10:45 AM EDT
Interesting article; thank you for that. The color pictures help a great deal. The difference between 1kHz and and 1 MHz is quite striking. What is the software that was used for these?
Sign in to Reply
Mark Fortunato
8/30/2012 3:35 PM EDT
Unfortunately Dr. Archambeault did not indicate what software he used for the simulations. If you go to the link to his write up on this (the second link for citation #3, above), he explains what he did. He also provides his email address there if you want to ask him directly.
Sign in to Reply
Mark Fortunato
9/26/2012 2:52 AM EDT
It turns out that Dr. Archambeault used an IBM-internal software tool for these graphics.
Sign in to Reply
Netteligent
8/31/2012 11:51 AM EDT
Thank you and look forward to see the next articles. Loving it.
Sign in to Reply
Jimbojet
9/4/2012 9:07 PM EDT
Doh! You are keeping me in suspense, waiting for the second installment! I hope it is released soon!
Sign in to Reply
Tucson_Mike
9/18/2012 8:07 PM EDT
Awesome stuff Mark. I love the return current pictures. I always love to get these boards in with the high speed amp decoupling off in a nice little grouping at the edge of the board - Countless re-spins have come out of that little EDA issue over the years. I'll look at parts 2 and 3 next, but the real interesting one I like is the impact of supply decoupling on HD2 when trying to push into the -100dBc region.
Sign in to Reply
Mark Fortunato
9/21/2012 5:57 PM EDT
Mike,
thanks for the props, old friend. So when are you going to write that article about decoupling effects on HD2? I'd be really interested.
Sign in to Reply
RAW666
12/17/2012 4:03 PM EST
Thank you Mark for the start of a valuable series. I am looking forward to the follow up installments. Most of my board designs over the years have been "mixed signal" and I rapidly learned that the only way I could achieve first pass success was to completely specify the exact routing and width of each and every trace. There is still too much tendency to consider a schematic as the "design" of a circuit.
Sign in to Reply
Juan Medrano
12/26/2012 10:24 PM EST
This is worth reading one time and another. For a beginner like me, I just feel hungry of more reading this and trying to understand it. Thank you so much Mr. Fortunato for such a great article!
Sign in to Reply