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Juan Medrano

12/26/2012 10:24 PM EST

This is worth reading one time and another. For a beginner like me, I just feel ...

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MSimon

12/21/2012 6:53 AM EST

I always use "too many" bypass capacitors in prototypes. It saves trouble. If ...

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# Successful PCB grounding with mixed-signal chips - Part 1: Principles of current flow

## 8/27/2012 10:05 AM EDT

To this point in our discussion of the basics, the model has been somewhat simplistic. We conveniently divided signals into low frequency and high frequency as if there were a well-defined boundary between the two.

The truth is that both paths are always involved. In Figure 6, at the initial transition of the IC1 output to the low state, the current comes from the bypass capacitor at IC2. This is because the output of IC1 is "demanding" a near-instantaneous current from the input pin of IC2, which pulls this current from its power pin.

We placed a bypass capacitor at IC2 with very short connections to its power and ground pins precisely to supply the fast current demands. The power source cannot provide this transient current as it is not very close to the IC and, thus, has substantial resistance and, more importantly, inductance between it and the power pin of IC2.

This is the whole reason for placing bypass capacitors at the ICs: to supply the transient (high-frequency) currents that the power supply cannot. As the transient settles out, more and more current comes from the power source and less and less comes from the bypass capacitor.

We simplify this concept further by saying that the DC current comes from the power source and the AC current comes from the bypass capacitor(s). We know, of course, that it is a bit more complex than this explanation.

As we consider more dynamic situations, we find that all the currents flow through a combination of the above four paths. The common path in either direction starts with the power pin of the sourcing component (IC1 or IC2), proceeds through that component and through the interconnect to the other component (IC2 or IC1), and then through the second component to its ground pin.

How the current completes its circuit from ground to the power pin of the sourcing component depends on the speed of the signal. The DC current will all return to the ground lead of the power source; it will flow from the power lead of the power source to the power pin of the sourcing component. High-frequency signal current will instead return to the ground lead of the sourcing component's bypass capacitor, which also supplies the current to the power pin.

In reality, both paths are always involved, with the DC path dominating for low-frequency signals. Keep in mind that even if a digital signal transitions at a slow rate (for example, a 1Hz square wave), the state transitions that cause the transient currents are just as fast as with a much higher frequency signal. They simply do not occur as often.

Of course, we are dealing with a good design here, so the bypass capacitors and the IC power and ground pins are very close. Proper bypassing like this makes a designer's job much easier. We can usually just think of the bypass capacitor and the IC as one entity when considering the flow of signal currents across a PCB.

Notice, finally, that the power current for high-speed AC signals travels a very short distance from a bypass capacitor to the IC that it is bypassing. The paths through the ICs themselves, of course, are short. The vast majority of the distance of the current loop is in the interconnect from the output of one chip to the input of the other and the ground return path.

Review Figure 4 and Figure 5 and consider what happens if the ICs are separated by a greater distance. The bypass capacitors stay close to their respective IC, and all the distance is added to the interconnect and the ground return. For higher-speed signal currents, this is where we will see problems…if they occur.

Kyle B

8/28/2012 10:00 AM EDT

Thank you Mark for one of the best explainations of this phenomenom that I've seen yet! I've seen this written many different ways, this paper is definitely a "keeper". I'll be using it to help train the "newbies" as we hire 'em :)

Looking forward to part II !!!!

Mark Fortunato

8/28/2012 7:29 PM EDT

Kyle, thanks for the kind words. I developed this appoach over the years of explaining it to customers and helping them make their designs work with our chips. Having to go over the same concepts many, many times helps to clarify one's understanding. Keep teaching those newbies and you will find yourself better understaning the stuff you are teaching.

MSimon

12/21/2012 6:53 AM EST

I always use "too many" bypass capacitors in prototypes. It saves trouble. If the design goes into production I like to see how much that can be reduced before trouble. It gives some idea about how much costs can be reduced. In the TTL wire wrap days with boards that were mostly power, ground, and sockets - one bypass capacitor (.1uF) every other chip was considered adequate. I would make that one every chip these days. Plus I add a 4.7uF (at low voltages) at every chip just to be sure. Backing off the on 4.7s for production.

BTW high speed digital is sometime prone to transmission line effects at distances as short as one inch. Depends on if you got a "good" (very fast) set of production chips. Note: delays on some of the faster chips are quoted as fast as .5nS. The edge speed goes up accordingly. It is the speed of the edge that matters. Termination (or capacitive loading at the source) can tame this. If you don't need speed don't use it.

CCarpenter

8/28/2012 2:07 PM EDT

I too look forward to the next installment. I think this series is going to be very helpful.

mtripoli

8/30/2012 10:45 AM EDT

Interesting article; thank you for that. The color pictures help a great deal. The difference between 1kHz and and 1 MHz is quite striking. What is the software that was used for these?

Mark Fortunato

8/30/2012 3:35 PM EDT

Unfortunately Dr. Archambeault did not indicate what software he used for the simulations. If you go to the link to his write up on this (the second link for citation #3, above), he explains what he did. He also provides his email address there if you want to ask him directly.

Mark Fortunato

9/26/2012 2:52 AM EDT

It turns out that Dr. Archambeault used an IBM-internal software tool for these graphics.

Netteligent

8/31/2012 11:51 AM EDT

Thank you and look forward to see the next articles. Loving it.

Jimbojet

9/4/2012 9:07 PM EDT

Doh! You are keeping me in suspense, waiting for the second installment! I hope it is released soon!

Tucson_Mike

9/18/2012 8:07 PM EDT

Awesome stuff Mark. I love the return current pictures. I always love to get these boards in with the high speed amp decoupling off in a nice little grouping at the edge of the board - Countless re-spins have come out of that little EDA issue over the years. I'll look at parts 2 and 3 next, but the real interesting one I like is the impact of supply decoupling on HD2 when trying to push into the -100dBc region.

Mark Fortunato

9/21/2012 5:57 PM EDT

Mike,

thanks for the props, old friend. So when are you going to write that article about decoupling effects on HD2? I'd be really interested.

RAW666

12/17/2012 4:03 PM EST

Thank you Mark for the start of a valuable series. I am looking forward to the follow up installments. Most of my board designs over the years have been "mixed signal" and I rapidly learned that the only way I could achieve first pass success was to completely specify the exact routing and width of each and every trace. There is still too much tendency to consider a schematic as the "design" of a circuit.

Juan Medrano

12/26/2012 10:24 PM EST

This is worth reading one time and another. For a beginner like me, I just feel hungry of more reading this and trying to understand it. Thank you so much Mr. Fortunato for such a great article!