datasheets.com EBN.com EDN.com EETimes.com Embedded.com PlanetAnalog.com TechOnline.com
Events
UBM Tech
UBM Tech

Design Article

#### Comment

Mark Fortunato

12/19/2012 12:12 PM EST

RAW666,

Very good point. My article was limited to using a two layer ...

More...

rembrandt

12/18/2012 7:04 PM EST

So on the Part 2 and Part 3 articles, the link for next page seems broken for me ...

More...

# Successful PCB grounding with mixed-signal chips - Part 3: Power currents and multiple mixed-signal ICs

## 9/17/2012 9:20 AM EDT

In Part 1: Principles of Current Flow, we began with the basics. We learned that high-frequency signals flow not in the path of least resistance, but in the path of least impedance. We also discussed some fundamental principles of current flow in PCBs with ground planes.

In Part 2: Design to Minimize Signal-Path Crosstalk, we applied those principles to real-world circuits and to the PCB layout of these circuits. We learned how to place components and route signal traces to minimize problems with crosstalk.

In this final Part 3 we consider the power source currents and how to apply what we have learned to circuits with multiple mixed-signal ICs. We finish with an example where a ground plane cut is useful.

At the end of Part 2 in our series we decided to eliminate the ground cuts in our example layout because there are no signal return currents that "want" to cross the cuts. We do, however, have to consider the power connections. If both analog and digital power is from the exact same supply, then the source and its return must be on one side of the cut or the other (Figure 1).

Figure 1: AC signal currents with proper routing. See Figure 8 in Part 2 of this series.

In this case all the DC return currents (and frequencies low enough that significant current comes from the supply and not the bypass capacitors) from the other side of the cut must funnel through the narrow ground bridge rather than going straight to the power return connection. This makes their path longer, the resistance that they encounter larger, and thus the voltage drops greater.

This layout is no problem for return ground currents where the pins on the ADC sink the signal current, because these currents return from the ground pins which are both at the bridge. However, currents from ground pins on other components have to take an indirect route. Figure 2 illustrates these currents.

Figure 2: DC ground currents with cuts.

Removing the Cuts
If we remove the cuts, the DC return currents can flow more directly, with lower resistance and thus lower voltage drops. Figure 3 shows the same ground currents but with the cuts removed.

Figure 3: Circuit of Figure 2 with the ground cuts removed.

The same thinking can be extended to the situation where there are multiple rails. We just have to remember where the return currents will flow and take the multiple rails into account, just as we have done with the single rail.

Haldor

9/19/2012 3:24 PM EDT

The discussion about component placement and keeping a solid ground plane are good.

Another equally important concept is connector placement. Ideally you would want to place all of the connectors along one edge of the PCB. Putting connectors on opposite sides of the board means create dipole antennas when you plug cables into those connectors. Any current flowing through the ground plane is going to create a voltage difference from one edge of the ground plane to the other. When you connect cables to those opposite edges of the ground plane, the plane ground noise is going to radiate out on the cable shields. That is the reason you so often see ferrite lumps on cables in order to stop the ground plane noise from radiating out on the cable shields.

Keep all of the connectors on the same edge of the PCB and you eliminate that situation entirely. If you need more connector space will fit on one edge of the PCB then put them on an adjacent corner of the PCB and don't put any noise radiating (or noise sensitive) components in that corner of the PCB.

Mark Fortunato

9/20/2012 2:54 PM EDT

Exccellent point, Haldor. Keeping all connectors on one side really helps. Unfortunatley sometimes there are harsh realities that prevent this from happening. This is another reason for planning mechanical things like connector placement in the earlier stages of a project. The earlier these things are considered, the more likely they are to be done right. If you wait too long the marketing guys will make these decisions for you. (I have been that marketing guy in the past).

Netteligent

9/20/2012 3:19 PM EDT

I regret not to have a chance to work with Jim Williams and Bob Pease. Fortunately, I have found Mark Fortunato with his brilliant mind in writing. You are my hero and hope to meet with you in person.

Mark Fortunato

9/21/2012 3:55 PM EDT

Netteligent. I am honored to be mentioned along with those two giants of EE applications engineering. I am not in their class but aspire to get as close as I can to their clarity and depth of knowledge when I write.

Todd Toporski

9/24/2012 10:08 PM EDT

Hi Mark, Nice work on this series of articles. The basics in article 1 is a good refresher for veterans and newbies. Grounding (article 3) has always been one of my favorite topics, and I couldn't agree more with using a single GND plane - with proper partitioning - for most circuits. I see far too many people getting fancy with GND splits for mixed-signal circuits, and the result is often degraded circuit performance or EMI issues. A single GND plane is the right choice for most circuits unless something like isolation or ultra low leakage currents is a requirement. Great job!

Mark Fortunato

9/26/2012 2:54 AM EDT

Todd, thanks for the props. It was exactly the kind of experiences you describe that is the ultimate genesis of these articles.

RAW666

12/17/2012 4:29 PM EST

Mark,

You have written a very valuable discussion of the current flow considerations. In general, the capacitive coupling also must be considered. I have seen many boards that had to be re-spun because of the placement of a single "digital" trace that was routed past a via connected to an op amp summing node. In very sensitive cases, the same problem could be caused by a digital power plane around such a sensitive node.

Mark Fortunato

12/19/2012 12:12 PM EST

RAW666,

Very good point. My article was limited to using a two layer board to help make the concepts clear. When you get to multi-layer boards with power planes then the desire to keep the digital away from the analog gets more complex. I also did not go into capacitive coupling in any detail as there is only so much that can be covered in the limited space.

rembrandt

12/18/2012 7:04 PM EST

So on the Part 2 and Part 3 articles, the link for next page seems broken for me ( stuck on Page 1 of 3 ) tried two different browsers - same behaviour. Anyone else having this issue? Part 1 was great btw.