Design Article
Analyzing audio DAC jitter sensitivity
Matt Felder, Patrick Gallagher, and Brian Donoghue, Maxim Integrated
9/29/2012 11:48 AM EDT
Jitter Tolerance Test Results
Figure 8. Dynamic range degradation with 11.5ns RMS cycle-skipped clock jitter.
Notice that the MAX98355 dynamic range does not degrade with the cycle-skipped jittered clock. The MAX98355 thus outperforms the “120dB DAC” by more than 20dB with the jittered clock.
Figure 9. Dynamic range degradation with broadband white jitter.
The 3.5ns and 5.9ns jitter performance for Competitor 3 as well as the 5.9ns jitter for Competitor 2 are extrapolated because the part does not actually function properly with those jitter levels; they start dropping bits and the actual measured dynamic range is lower than shown in this plot.
Figure 10. 1kHz THD+N performance degradation with clock jitter.
Figure 11. 20kHz THD+N performance degradation with clock jitter.
Conclusion
This article has presented a methodology for testing audio DAC jitter tolerance. Audio DACs respond differently to jitter in the low-frequency and high-frequency bands, thus it helps to separately specify tolerance to these two bands of jitter spectrum. DACs that tolerate high levels of jitter allow simpler implementations of the sampling clocks without degrading audio quality.
About the Authors
Matt Felder joined Maxim Integrated in 2009 as an analog design engineer. His work includes audio DACs, audio ADCs, multichannel SAR ADCs, headphone amps, a video DAC, an FM radio receiver, and a multiformat battery charger. Matt is a senior member of the IEEE® and has 35 issued patents. He has a BSEE from Texas A&M and an MSEE from UT Austin.
Patrick Gallagher received a B.S. in Electrical Engineering from Texas A&M University in 2008. He joined Maxim’s Audio Group immediately after graduation. Currently, he is a Product Engineer with expertise in automated test and measurement.
Brian Donoghue worked as a product engineer at Maxim Integrated from 2007 to 2012. His work included bench characterization of precision amplifiers, audio amplifiers, audio CODECs, video ADCs, video filters, and LCD gamma references. He has a BSEE from Texas A&M University.
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rsiggelkoe
10/2/2012 6:05 PM EDT
Jitter tolerance is a nice feature, but in the real world, no one who buys a (relatively) expensive 120-dB DAC would drive it with such highly jittered clocks. Your comparison is valid for some very low cost designs I suppose, but in most instances a proper low-jitter audio clock source is trivially easy to generate.
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matt_felder
11/16/2012 10:34 AM EST
The 120dB DAC was included to show that even a very high end DAC would not match the jitter tolerance of the Maxim DAC. The parts chosen for the comparison were competitor DACs that specifically touted a high level of jitter tolerance. In the price sensitive consumer audio market there are situations where creating a clean sample clock cannot be accomplished without adding more silicon area, extra pins, extra clock references, or extra power. All of which are undesirable. A clean sample clock can be specified for a system at a cost that may not be trivial. A substantial number of audio products currently on the market have jitter-limited dynamic range performance.
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