Jitter Tolerance and Clock Generation
Jitter Tolerance and Clock Generation
Digital-input Class D audio amplifiers do, admittedly, present a new challenge for clock jitter. For good audio quality most digital-input amplifiers require fairly low levels of jitter on BCLK or PDM_CLK. The jitter tolerance is often not quoted in the data sheet; when jitter tolerance is quoted, the typical specification is ~200ps of RMS jitter. High levels of clock jitter will typically degrade either the amplifier’s dynamic range or the full-scale THD+N performance.
In many systems the reference oscillator for the application processor is not a convenient multiple of the PDM_CLK or BCLK, so providing a low-jitter clock for the amplifier is not easy. For example, 13MHz is a common crystal frequency used for GSM phones and 27MHz is commonly used in video solutions. Neither of these reference frequencies is a convenient multiple of the 44.1ksps or 48ksps audio sample rates. These systems will, therefore, often implement a complicated fractional-N PLL to create the clock for the audio. In some cases, the solution will require a separate audio reference oscillator which increases complexity and bill of materials (BOM).
An alternative, and preferable, solution is a digital-input amplifier that can tolerate very high clock jitter without degrading the audio performance. Such an amplifier will reduce system complexity. In the simplest case, a cycle-skipping clock can be used to generate the PDM_CLK or BCLK, but this generates extraordinarily high jitter. If a 13MHz reference clock is cycle skipped to create a 6.144MHz PDM_CLK (48ksps x 128OSR), then the peak jitter will be 38.4ns and the RMS jitter will be 22.2ns (Figure 4).
This represents two orders of magnitude higher jitter than most DACs can tolerate. The MAX98355 PCM and MAX98356 PDM Class D audio amps, however, still produce near 100dB dynamic range performance with this amount of clock jitter. A cycle-skipped clock can be created with a very small number of digital gates on the application processor. They do not need the oscillator or a loop filter that would otherwise be required in a PLL solution. See Figure 5.
Figure 4. A 12.288MHz MCLK from a cycle-skipped 25MHz clock.
Figure 5. Fractional-N PLL vs. cycle-skipped clock implementations.
Jitter Tolerance Test Results
Test results show that the MAX98355’s dynamic range does not degrade with the cycle-skipped jittered clock. The MAX98355 outperforms the “120dB DAC” by more than 20dB with the jittered clock. Further details on jitter tolerance in sigma-delta DACs can be found in a companion article.1
Figure 6. Dynamic range degradation with 11.5ns RMS cycle-skipped clock jitter.
Digital-input filterless Class D audio amplifiers like the MAX98355/MAX98356 allow simple board-level implementation, a low BOM, high efficiency, low EMI, and high output power. These amplifiers are available in a 1.345mm X 1.435mm, 9-pin WLP package and produce as much as 3.2W of output power.
1 For more details, see companion article by Matt Felder, Patrick Gallagher, and Brian Donoghue, “Analyzing audio DAC jitter sensitivity,” EDN Network, September 29, 2012.
About the Authors:
Matt Felder joined Maxim in 2009 as an analog design engineer. His work includes audio DACs, audio ADCs, multichannel SAR ADCs, headphone amps, a video DAC, an FM radio receiver, and a multiformat battery charger. Matt is a senior member of the IEEE® and has 35 issued patents. He has a BSEE from Texas A&M and an MSEE from UT Austin.
Evan Ragsdale joined Maxim in 2011 as a Strategic Applications Engineer. He works involved wide-ranging design and evaluation of audio solutions for mobile products. Evan has a BSEE and a BA in Music Industry and Technology with an Option in Recording Arts, both degrees from California State University, Chico.