Figure 2 PWM signal
Figure 2 shows how a PWM signal is formed from the comparator (see comparator block in Figure 1). The analog input is compared to the 250-kHz triangle wave. When the analog input voltage is greater than the 250-kHz triangle wave voltage, the non-inverting class-D output is high. When the 250-kHz triangle wave is greater than the analog signal, the non-inverting comparator output is low.
The inverting comparator output is low when the non-inverting comparator output is high, and high when the non-inverting comparator output is low. The average PWM non-inverting output voltage, VOUT+(AVG) is the duty cycle times the supply voltage, where D is the duty cycle, or on time, t(ON) / total period, T.
VOUT+(AVG) = D * VCC (Eq. 1)
D = t(ON) / T (Eq. 2)
The duty cycle of the inverting output, VOUT–, is one minus the duty cycle, or 1–D, of VOUT+. If the input is at mid-supply, the duty cycle of VOUT– and VOUT+ is 0.5. However, VOUT– is not used in this design since the design is single-ended for simplicity and lowest cost.
Figure 2: Class-D PWM generation waveforms.
The class-D amplifier needs to have a wide enough bandwidth for the signal needed. If a DC waveform is desired, the class-D amplifier needs to be able to operate without input coupling caps. The TPA2006D1 is an example of a class-D amplifier with greater than 20 kHz bandwidth and can be DC-coupled so an AC or DC signal can be used. The gain is 300 k/Ri, where Ri is the input resistor, which is based on trimmed internal 150 kOhm front-end feedback resistors, and double the power-stage gain. The internal trimmed resistors with external input resistors make it convenient in setting the gain, depending on the input range.
The error in system output is due primarily to timing, since we are using a PWM. The class-D amplifier outputs a 250 kHz square wave with very accurate timing to minimize distortion and noise. However, the digital isolator needs to be much faster than 250 kHz. It must be able to switch fast enough for the rise and fall times to have as little effect as possible on the average output voltage and allow accurate low and high duty cycles. The digital isolator needs to have a propagation delay with rise and fall times much lower than the smallest desired on and off times, not just the period of PWM.
The rise and fall times, and prop delay low-to-high and high-to-low also should be close to the same. For example, if the rise time is much slower than the fall time, the output is shifted lower than intended because the output duty cycle is effectively reduced. This limitation is caused by using an optical-isolator in this solution. We chose the ISO721 for this design because the propagation delay for both low and high transition is 10 ns, and rise and fall times are equal at 1 ns. The ISO721 is only a single channel, but a dual, triple or quad channel from the ISO7xxx family can be used, if more isolated signals are needed.