RF DACs simplify power and space in downstream cable transmitter systems

The AD9129 RF DAC is sampled at rates as high as 2.8 GSPS. The advantage of such a high sampling rate is that the DAC images are folded around a higher f_DAC/2 than previous solutions. This prevents the images from folding below 600 MHz, easing the requirements for their suppression. The data is transferred into the DAC via a dual LVDS port clocked at up to 700 MHz, with data being clocked in on both edges of the clock for a 1.4 GHz data transfer rate over each port.

The current-steering architecture ‎[3] and careful design of the DAC enable superior spurious performance and a low noise floor. The DAC is implemented in a 0.18 m CMOS process, giving low power consumption of about 1.1W.

Between the DAC and amplifier, passive signal conditioning can help meet DOCSIS specifications for out of band rejection and power variation across the cable band. In the example design, a 7^th order elliptical filter was chosen to address the issue of out of band rejection. The AD9129 DAC’s lower sample rate of 2.305 GSPS was used in evaluation of the low pass filters out of band performance, since the images fold closer to the cable band with the lower sample rate.

The image for a 1 GHz channel was of particular concern, since it lands at 1.3 GHz, only 300 MHz away from the desired signal. The design achieved 62.5 dBc of image rejection for the 1.3 GHz image, meeting the DOCSIS specification for out of band rejection.

Two series resonant equalizer tanks were used to address the issue of power variation across the cable band due to the sinc rolloff at the output of the DAC and additional rolloff in the power amplifier. The equalizers achieved a power variation of about 1.4 dB between the highest power channel and lowest power channel in the band, meeting DOCSIS specs without any digital manipulation of the input signal. The power of each individual channel can be adjusted digitally to achieve a finer tuned flatness across the band.  

The TAT2814 output amplifier combines three functions into a single package, greatly reducing board space with the high level of integration. The amplifier delivers a total possible gain of about 30 dB. The output is capable of delivering up to +65 dBmV of power for a 1-channel 256-QAM signal. The amplifier is implemented in a GaAs process and is optimized for low power operation. The total power consumption of the integrated device is about 4.2W.

Non-Linear Correction (NLC) is used to improve the in band harmonic performance of the full signal chain, correcting distortion that comes from the DAC as well as from the power amplifier and any other distortion which may occur along the signal chain. The NLC process can be programmed to bring the board to meet specifications, or to allow for a specified margin to allow for manufacturing tolerances. NLC calibration only takes minutes and can greatly improve a system’s performance.

A board was designed with the AD9129 in an optimized layout, and its performance was measured. A signal with all 158 channels was used to test the flatness of the board’s response across the cable band. Figure 2 shows the optimized board’s output with the full band signal as the input. The power variation between the highest and lowest power channels is only about 1.4 dB, within the DOCSIS specifications and can be further improved with digital manipulation of the input signal.

Figure 2. Full cable band of 158 DOCSIS 256-QAM channels at the output of the example design

Tests show that boards can be reliably corrected with 4 dB of margin, making the system robust against manufacturing tolerances. Figure 3 and Figure 4 shows the performance of the second and third harmonic with NLC for 4 carriers. In the plots, the blue line represents the DOCSIS specifications. The data was taken with 2304 MHz as the DAC update rate.

Figure 3.  Four Carrier Second Harmonic Performance with NLC

Figure 4.  Four Carrier Third Harmonic Performance with NLC

Cable systems are being upgraded to support the rapid increase in demand for data services, and reduced space and power consumption are key drivers for new designs to accommodate more channels. RF DACs such as the AD9129 are enabling equipment suppliers to achieve new levels of channel density while delivering smaller size and lower power consumption.

About the authors

Daniel E. Fague is the Applications Engineering Manager in the high speed digital-to-analog converters group at Analog Devices. He received his BSEE from Gonzaga University in 1989 and his MSEE from the University of California at Davis in 1991. He joined Analog Devices’ wireless handset group in 1995 where he focused on handset radio architecture design, including direct conversion radios, for GSM, EDGE, CDMA, and Bluetooth. Prior to that, he worked for 5 years at National Semiconductor doing radio architecture design for DECT and PHS. He holds 7 patents and has published more than 30 articles and papers.

Sara C. Nadeau is a senior at University of Maine. She is studying Electrical Engineering with a focus in communications. She worked as an intern in the High Speed Digital-to-Analog Converters group at Analog Devices during the summer of 2012. She will graduate with a BSEE in May of 2013.