The following is Chapter 21 "Composite Amplifiers" from Linear Technology's Volume II book entitled, "Analog Circuit Design--Immersion in the Black Art of analog design" by Bob Dobkin and the late-Jim Williams published by Elsevier/Newnes.
This book is a great companion volume to Volume I with informative application notes and a full complement of reference designs. The chapters are not just every day application notes and reference designs, but give insights to problem-solving, design decision-making the thought process that goes along with a robust, successful design. That's why I love this book. The authors, Bob Dobkin and the late Jim Williams
(Along with the research and writings of Carl Nelson and Bob Widlar), have a rich history and depth of experience that they share with the readers. This book is a keeper that needs to be on every designer's bookshelf, right next to Volume I.
I have used composite amplfiers very successfully in many, many of my designs in the past 40 years with great success. Sometimes you just can't get exactly what you need in a particular design with just one op amp. A composite design, if done well, can add great performance to your overall system and the following chapter 21 tells you how to do it right.Composite Amplifiers
Amplifier design, regardless of the technology utilized, is a study in compromise. Device limitations make it difficult for a particular amplifier to achieve optimal speed, drift, bias current, noise and power output specifications. As such, various amplifier families emphasizing one or more of these areas have evolved. Some amplifiers are very good attempts at doing everything well, but the best achievable performance figures are limited to dedicated designs.
Practical applications often require an amplifier that has extremely high performance in several areas. For example, high speed and DC precision are often needed. If a single device cannot simultaneously achieve the desired characteristics, a composite amplifier made up of two (or more) devices can be configured to do the job.
Composite designs combine the best features of two or more amplifiers to achieve performance unobtainable in a single device. More subtly, composite designs permit circuit approaches which are normally impractical. This is particularly true of high speed stages which may be designed with little attention to DC biasing considerations if a separate stabilizing stage is employed.
Figure 21.1 shows a composite made up of an LT1012 low drift device and an LT1022 high speed amplifier. The overall circuit is a unity-gain inverter, with the summing node located at the junction of three 10k resistors. The LT1012 monitors this summing node, compares it to ground and drives the LT1022’s positive input, completing a DC stabilizing loop around the LT1022. The 10k-300pF time constant at the LT1012 limits its response to low frequency signals.
The LT1022 handles high frequency inputs while the LT1012 stabilizes the DC operating point. The 4.7k-220Ω divider at the LT1022 prevents excessive input overdrive during start-up. This circuit combines the LT1012’s 35µV offset and 1.5V/°C drift with the LT1022’s 23V/µs slew rate and 300kHz full-power bandwidth. Bias current, dominated by the LT1012, is about 100pA.
Figure 21.1 • Basic DC-Stabilized Fast Amplifier
Figure 21.2 is similar, but uses discrete FETs to more than triple the speed. Here A1’s input stage is turned off by connecting its inputs to the negative rail. The differentially connected FETs bias the second state via A1’s offset pins. This connection replaces A1’s input stage, reducing bias current and increasing speed. FET mismatch would normally result in excessive offset and drift. A2 corrects this by monitoring the summing point (the junction of the two 4.7k resistors) and forcing Q2’s gate to eliminate overall offset.
The 10k-1000pF pair limits A2’s response to low frequency, and the 1k divider chain prevents overdrive to Q2 on startup. The 1k-10pF damper at the summing node aids high frequency stability. Figure 21.3 shows pulse response. Trace A is the input and Trace B the output. Slew rate exceeds 100V/µs, with clean damping. Full-power bandwidth is about 1MHz, and the input bias current is in the 100pA range. DC offset and drift are similar to Figure 21.1.