We began the development with the USB interface. The USB specification itself is not particularly complicated, but we came to understand that the real problem is the software that comes loaded on the PC. Even if a USB-DAC meets the USB specification, it is useless if it will not operate under Windows or Mac OS.

There actually exist USB speakers that will not work (don't make a nice sound) with certain PCs. Even though these USB speakers fulfill the USB specification; that alone is not enough.

Obviously, certain know-how is necessary in dealing with interfaces. In LSI development we recognize that the use of previously-developed cores is the key to effectiveness. But we recognize that it is not always a simple matter to use an existing core even when dealing with a standard interface. In that sense, the decision of whether to use existing cores is very important. Certainly there are cases where an existing core could be used but the cost is too high to make business sense.

With this in mind, we tested that actual operation of a PC using a large-scale PLD.

Using a Large-scale PLD We Decided to Develop a USB Core

First we mocked-up a system containing a PLL and a DAC and tested the operation on various PCs. Using as cores a PLL1700, a PLL chip with a high Carrier/Noise (C/N) performance specification, and a PCM1716, a well-known 96 kHz - 24 bit DAC, we were able to use a PLD to efficiently test the USB operation. Use of the PLD allowed us to observe internal signals and test conditions that do not actually occur. This is particularly useful when communicating with PC software, as in our present case.

A FIFO is Used to Deal with Packets that are not in Order

USB sends audio data packets on 1 ms intervals. Since, as mentioned previously, pauses in the audio cannot be tolerated, audio playback begins when the first packet arrives, and the next packet must arrive before all of the data in the previous packet has been played. Although we are discussing audio packets in particular, it is possible for the order of packets to be disrupted by other USB packets. In other words, a FIFO large enough to hold at least two packets is required to deal with the possible change of order.

In the case of dealing with 48 kHz, 16-bit stereo data, the buffer capacity must be at least 48 x 16 x 2 x 2 = 3,072 bytes. However, since we know that FIFOs require significant die area, we want to make them as small as possible to save cost.

USB Clock Error Uses up the FIFO!

On the other hand, the USB specification allows for clock frequency error of 500 ppm. This is an easy-to-accomplish specification for a crystal oscillator and makes the design of the USB circuitry rather easy. However, this is an allowance for an error between the send and receive clocks, and poses a problem for audio.

In this case, the read and write clocks for the FIFO are different. As the 500 ppm error accumulates, the 1 packet buffer margin will be completely used up in 2,000 packets. Since 1 packet is 1 ms, 2,000 packets works out to 2 seconds. If one packet is lost and the device jumps to the next, a popping sound will be heard.

A Clock Tracking PLL Circuit is Essential

It would never do to create a DAC that makes noises every few seconds, or even every few dozen seconds, depending upon the clock precision. In order to avoid this, it is necessary to have the receive clock track the send clock.

For this reason we determined that it is necessary to have an excellent C/N performance PLL on the chip. Although this might mean a cost increase, it must be done. At this point any hope of using a standard USB core was completely eliminated.

4. Test Chip Development

The Capabilities of the First Test Chip

We decided to develop a single chip containing a USB core, a DAC, and a PLL. It was determined that we would use our existing DAC and PLL cores.

By integrating the PLL, we were able to develop a USB-DAC that did not make popping noises. At such a time it is human nature to want various people to see (hear) the result, so we demonstrated it to all of those purported to be 'Golden Ears.' The audio signal came through the PCM1716, a DAC with an industry-wide reputation, and the PLL as the PLL1700, which has excellent C/N performance.

Since Windows 98 has a 48 kHz, 16-bit limit for audio data, at first glance it would appear that the 96 kHz - 24-bit PCM1716 was over specified for this task (please see Personal Sidebar B). But inside this chip the bit rate is oversampled by a factor of 8, and the precision increases to 24 bits. I thought the sound performance was sufficient.

The Distortion is an Order of Magnitude too High you say?! Why....?

When the guys in charge listened to the prototype I saw dubious faces and was asked a variety of questions such as "Is the source coming from the PC corrupted?" In the end I was told to measure the audio performance. When I announced the results in a subsequent meeting I was told the distortion was an order of magnitude too high; the THD+N was 0.03%.

I wondered what was wrong with 0.03%, but was told that "We could never sell a device with this performance as one of our own."

For a 16 bit, 48 kHz system, I would have to achieve at least 0.003%!

I was faced with (attacked by) a problem. Some asked, "Is the digital data getting corrupted somewhere?" But rigorous VHDL simulations did not locate such a bug. For the first time I had the feeling that analog is awful...

I went into this thinking "Since we are processing digital signals, we can expect good sound as a matter of course, and from here on we are dealing with digital!" So this experience was a real shock.

"Is noise getting in to the signal somewhere? Maybe it's crosstalk through the signal lines. Or is there a timing problem with the data transmission?"

Troublesome thoughts, day after day.

I'm Responsible for Tracking Circuitry? Let's First do an FFT Analysis.

As the person in charge of tracking circuitry, I was praying (?) that there would be a bug in the digital system somewhere. This is because previous experience had taught me that it can be difficult to tune a tracking circuit. And there are stability issues as well. I was afraid the development effort would drag on. Because of this I first did an experiment to prove that there was no problem with the tracking circuitry. Since we have distortion, we should be able to see something on an FFT.

So I did an FFT analysis using the Audio Precision. From the USB port I output a full scale, 1 kHz signal with a sampling rate of 44.1 kHz. Since there could be some strange components, I looked at the spectrum out to about 70 kHz.

This spectrum is shown in Figure 7. The 1 kHz fundamental is fine, but there are also noise or distortion products. The frequency characteristic that results from the Delta-Sigma DAC's noise shaper can be seen as the noise floor rises after about 40 kHz, but there are no strange components in the 40 kHz to 70 kHz region. However, this is certainly a shape that one does not often see. The noise floor is pulled up to about 105 dB and there are broad skirts around the signal.

Figure 7. Full-scale Signal FFT of First Prototype (Noise floor has risen to around 105 dB)

Figure 8. FFT Analysis with Tracking On/Off (Noise floor rises -123dB to -118dB due to tracking.)

Next I investigated whether there was any difference with the PLL tracking turned on versus when it was turned off. Since the internal circuitry follows the clock, even for a zero signal input, we should see noise as a result of the fluctuations in the bipolar zero level if the clock is fluctuating. Figure 8 shows the FFT result (noise floor) for a zero input in the cases where the tracking circuit is On versus when it is Off.

Of course, an experiment like this can be done without having to solder or go through other manufacturing steps; the PLD can make very surprising contributions to the development. It's hard to imagine doing development without using a large-scale PLD. Since it was hard to see at a glance, I plotted the On and Off cases five times each. In the 200 Hz to 30 kHz region, the noise floor rose from -123 dB to -118 dB. There still remains the question as to whether tracking alone can cause this much change, but, in any case, this did confirm the fact that some degree of change was present.

Upon Raising the FFT Resolution . . . A 100 Hz Monster Appeared!

Next, in order to investigate the skirt around the fundamental, I decided to increase the FFT resolution to a higher setting than I usually use. Naturally it took longer to make the measurement. After a wait time that would best be measured in a fractions of an hour, I was amazed at the FFT analyzer's output graph. The measured FFT is shown in Figure 9.

Figure 9. New FFT with Higher Resolution

It was completely opaque from the lower-resolution FFT, but at this higher resolution, the figure looked like a chestnut that had sprouted sea urchin-like spikes. It was an impulse train with spacing of exactly 100 Hz! Since the noise floor under conditions of no input signal is flat, this appears as signal distortion. If the frequency response shows an impulse train, the time waveform will also contain a 100-Hz impulse train.

The True Character of the 100 Hz Impulse Train...

Even for a sample rate of 44.1 kHz, the USB isochronous mode packets have a period of 1 ms (1 kHz). In order to distribute 44.1 kHz across 1 ms intervals, one 45-sample packet is sent for every nine 44-sample packets. The tracking pulse (as we will call it here) for every 45 sample packet occurs once every 10 packets, or with a frequency of 100 Hz. Since the PLL loop filter, a so-called low pass filter, has its corner in the tens of kHz range, this 100 Hz tracking pulse goes right on through and shows up on the PLL's VCO control voltage. It appears as frequency jitter.

From the graph it is seen that the PLL frequency fluctuates impulsively right at 10 ms intervals. As a test I changed the sampling frequency to 48 kHz and measured the same 1 kHz signal.

Upon Changing the Sampling Rate to 48 kHz...

This time, since each packet always contains 48 samples, there should be no 100 Hz tracking pulse.

Figure 10 is the FFT for this case. The 100 Hz impulses have certainly disappeared, but some weak 142 Hz pulses have appeared in their place. And there is a succession of lobes. This is probably the result of phenomenally excessive ringing that goes along with the tracking operation!

Figure 10. FFT for 48 kHz Sample Rate

The impulse-type artifacts are a result of the open loop gain being high (due to the cost priority, a minimum-sized buffer is used and the gain of the tracking function is set high). It seems that we have a problem for a control theorist (this was my college major). However, increasing the buffer size and decreasing the gain only caused a low frequency disturbance on the signal and did not turn out to be a viable solution.

The Terrors of the Isochronous Mode

We still have a problem. It is a problem with a USB mode: in the adaptive isochronous audio transmission mode, the receiver has to determine the bit rate. This means that the bit rate is unknown prior to the time the data arrives.

The bit rate cannot be known prior to actually observing the packet.

Another terror of USB is that, according to the specification, it would not be unusual for the bit rate to change when the operating system is busy. Since the packets arrive on 1 kHz intervals, the PLL must lock within 1ms. In most PLLs, if we say that 1 kHz fluctuations are clearly audible and decrease the gain, we cannot track! Terror of terrors, we have just bumped into a brick wall. Upon doing some investigation, we were actually able to observe fluctuations in the audio frequency characteristics of one company's USB-DAC. Upon listening this could be detected as a disruption in the rhythm of the music. In reality, fluctuations in the time domain will probably result in an unpleasant listening experience. This is probably because they are delaying the lock-up time in order to reduce the jitter distortion.

Also, for isochronous USB data, a buffer is necessary for the time between the beginning of the packet until PLL lock, so the PLL lock-up time is reflected directly in the chip cost. The more audio quality is pursued, the longer the necessary buffer and the longer the time lag when playback begins. On the other hand, if the time constant of the loop filter is increased, a large RC is necessary and the chip area increases (recent progress in semiconductor technology has brought about minimization of digital devices, but analog devices have not changed).

If an external filter is needed, not only does the part count increase, but the board area also changes making the total cost increase significantly...

5. Delta-Sigma DACs and Jitter Control

The Advantages of Delta-Sigma DACs

Recently Delta-Sigma DACs have become the most popular type. At my company this is true at least for the lower-cost products. It is not my intention to give a primer on Delta-Sigma DACs, but to state it simply, this is a method of re-creating analog data using a one- or multi-bit Pulse Density Modulation (PDM).

Earlier DACs re-created analog signals using resistor ladders and the like. But, as the bit precision became higher, the errors in resistive ladders, as well as the current leakage, made it difficult to minimize semiconductor devices using these technologies. In the PDM used by Delta-Sigma DACs, the voltage and current are not controlled by controlling the combinations of resistors. Instead, integrators are used and the analog signal is re-constructed by controlling their charge times. It is basically the same as in the 1-bit Pulse Width Modulation (PWM) based DACs used in motor control. However, since the error is integrated, the precision is greater even for the same time resolution. The Burr-Brown PCM1716 is a charging-type, enhanced multilevel Delta-Sigma DAC that uses 8 times oversampling and 8 analog levels to achieve higher precision than 1-bit DACs.

The Disadvantages of Delta-Sigma DACs - Jitter Control

When considering ladder resistance error and current leaks, Delta-Sigma DACs certainly have a time control advantage given the exceptional precision of crystal oscillators. However, it must be remembered that they also require low jitter.

In usual circumstances this is not a big problem. However, as in the present instance, system clock tracking pulses, if they are needed, appear directly as signal distortions. This is not limited to USB, but will definitely be a problem for all digital transmission devices.

For example, since the receiver clock has to track the sender clock when a digital cable, in other words an SPDIF optical cable, is used to connect a CD player to the amplifier, the tracking pulses on the receiver clock will be a source of distortion. Of course this problem can be masked using digital filters and the like, but, since it decreases performance, it is not ideal for audio applications.

In other instances too, for example in products where tracking is used to synchronize image and sound data, signal distortion occurs as a result of the PLLs used. Care must be taken since this distortion will not be found characterized in data sheets. It appears that there are some systems in which the image frame rate is adjusted instead of the audio, to make the adjustment less noticeable (human eyes are not as sensitive as human ears, so if 2 or 3 frames of video information is dropped, it will not be noticed).

Back to the Beginning

We took a detour but now the USB-DAC development has come full circle. If we are to adopt an expensive, multi-level DAC, we will have to go back and re-investigate the marketing situation.

Feedback Control Doesn't Cut It

Since it is useless to be continually bewildered, I decided to reopen the tracking experiments. I adjusted the gain with an eye on the jitter analyzer. But I did not find a solution that satisfied the jitter and lock-up time requirements for an audio device. The biggest problem is that the 1 kHz feedback frequency is smack dab it the middle of the audio range. If the loop filter characteristic is shifted toward the low end the lock-up time become too long. If the PLL loop filter does not receive a reference signal for several clock cycles, it does not lock.

For several days I debated this within my own head: "If I don't use feedback the sound skips. If I do, distortion arises..."

I Try Feed-forward Control

And then, finally, I thought, "Wait! If I use feed-forward I'll bet they'll be no distortion!" At a time like this a PLD is certainly handy. No matter what the algorithm, as soon as it is written in VHDL it can be tested. In the days where silicon was fabricated based only upon simulations, the cycle time was so slow it was probably difficult to even entertain the notion of doing experiments!

Simulation is also a useful technique, but the test bench is, of course, written by humans. Missed hypotheses are never forgotten, and since the answer is often close to that desired by the experimenter, most folks probably find unexpected peace of mind. I think that people who feel relief because they simulated something are probably over confident or a little slow. At any rate, I can't feel good about a design until I have actually built and tested the circuit.

I Achieve Low Distortion, but...

But, for feed-forward control, the one side must be able to specify the frequency of the other. However, since this is an experiment, I tried a two-pass approach. The FFT became unbelievably clean. The THD+N was 0.003%. I arrived abruptly at the goal.

However, lock-up takes 5 seconds!

"When I evaluate a 1 kHz signal the frequency counter digits continue to change... When I listen on a speaker the sound continues to change. There's nothing to do now but laugh!"

And in the instant after thinking that, I began beating my head with a hammer for the second time.

6. An Honored Professor and a Time-optimal PLL

Seeking Advice by E-mail

The Internet is essential to current research and development activities. This is because it allows discussion even without meeting face-to-face. Sometimes very beneficial advice from others can be found through e-mail. This is because different points of view or conceptualizations can be an opportunity to break a deadlock.

I sent e-mail to my professor from the university and to a fellow student from the research lab. The former is Professor Fuminori Kobayashi of the Kyushu Institute of Technology. He is jointly researching PLLs and motor rotation distortions so I expected some good advice. The latter, Hidekazu Machida, teaches at the Maizuru National College of Technology. When I told them, "I am looking for a fast lock-up time PLL," Professor Kobayashi said, "How about some papers I wrote 20 years ago on 'Time-optimal PLLs'?" and sent me several papers. Mr. Machida, who was copied on my message, pointed out that "the lock-up time is short but the jitter performance is bad." But since this is the first step, I put this method into the PLD and began the experiment.

The Time-optimal PLL Passes the Lock-up time Test but...

The conclusion regarding the Time-optimal PLL is that its lock-up time performance is extraordinary. Due to the structure of a PLL, it cannot measure the frequency in less than two reference clock cycles. But the PLL of Professor Kobayashi's paper is locked perfectly by the third clock cycle.

However, the jitter performance, as suggested by Mr. Machida, did not meet the specification. The result of tuning up the circuit, using the PCM1716, was a THD+N of 0.01%. This is a factor of 3 lower than the original THD+N of 0.03%, but still a long way from the desired 0.003%.

But I had a feeling that it might just be possible to make this work. If this algorithm is used, the buffer can be the minimum size. Now just to start with this research as the basis and try to improve the jitter performance. In other words, the desire was to use the Time-optimal PLL and gets its jitter performance into the range of crystal oscillators.

Actually, even as I read the PLL papers I had the intuition that the feed-forward concept could still be put to use. That intuition turned to conviction as I tested the PLL algorithm. In order to lock to the connected device in minimum time, the connected device's frequency must have been estimated. This was the birth of SpAct (s-pact).

We will discuss those results after a discussion of the principles behind the Time-optimal PLL.

Principle of Operation of the Time-optimal PLL

Figure 11 is a top-level timing chart to explain the principle of the Time-optimal PLL. This figure depicts the following: (a) The PLL's reference frequency. (b) The VCO's waveform (oscillator frequency/phase) when the PLL responds in minimum time. (c) The output waveform of the phase comparator (phase error) given the above two reference signals.

Figure 11. Principle of Operation of the Time-optimal PLL

Figure 12. PLL Loop Filter Structure

Now to explain the operation. Figure 11 shows the response when the reference clock period changes from T1 to T2 at time t0: (1) Until time t0 the PLL is locked and the phase error is zero. (2) At time t0, immediately after the period of the signal changed from T1 to T2, since the phase comparator is not yet cognizant of the sender's period, the VCO's control voltage stays the same as before. (3) Next, the VCO output acknowledges the comparator at t1. (4) Then the evaluation of the phase comparator's error begins and is completed by time t2. We can see from the figure that the phase error measured at this point is T2 - T1.

The Time-optimal PLL exploits this single error to lock, as shown in the response in (b), at the next sample point, t3.

The Transfer Function is Derived from the Phase Error Next we shall derive the transfer function between the phase error in Figure 11 (c) and the response of Figure 11 (b). We can represent the signal of Figure 11 (c) using Sequence 1: ..., 0, 0, T2 - T1, 0, 0, ... (Sequence 1)

The Time-optimal PLL's response of Figure 11 (b) can be represented as a time sequence by Sequence 2: ..., T1, T1, 2T2 - T1, T2, T2, ... (Sequence 2)

Sequence 3 is derived by taking the difference of neighboring elements in Sequence 2: ..., 0, 0, 2(T2 - T1), -(T2 - T1), 0, ...(Sequence 3)

Here, by studying Sequences 3 and 1 the following can be discerned: Sequence 3 can be created from Sequence 1, the phase error signal, alone. Use a doubled Sequence 1 (Sequence 4) and a one-sample delayed Sequence 1 (Sequence 5). Now, invert the signs and add. In other words, this can be implemented using a multiply by 2 and a difference.

..., 0, 0, 2(T2 - T1), 0, 0, ... (Sequence 4) ..., 0, 0, 0, T2 - T1, 0, ... (Sequence 5)

Sequence 3 integrated [1/(1-Z^-1)] is Sequence 2, the Time-optimal PLL's response we were trying to derive. The transfer function that takes (c) to (b) is:

The block diagram that implements this is found in Figure 12. Here, e(k) is the phase error output from the phase comparator, and u(k) is the VCO set voltage (frequency/phase).

The left side of Figure 12 shows the multiply that doubles the error; Z^-1 is the unit delay element. Also, the right side of the figure shows the integrator that returns Sequence 2 when Sequence 3 is applied.

The Time-optimal PLL's loop filter can be realized with this simple circuit. (Actually, as for the basic structure, it is necessary for the phase comparator through the VCO gain to be strictly identified in a physical sense.)

7. Completion of the Control System - The Extended Time-optimal PLL

The Problem is the PLL Loop Filter

First let's make it clear where the problem lies. The problem is with the PLL loop filter. This is basically a low pass filter and its cut-off frequency determines the PLL lock-up time. Since the base of a PLL is typically considered to be a crystal oscillator, when jitter performance is questioned, the problems typically occur at high frequencies. Because of this, a low-pass filter that sufficiently attenuates high frequencies is designed. Since the tracking performance or lock-up time is determined by the lower frequencies, the gain at these frequencies is set moderately high.

The problem is in cases where the receiver tracking frequency enters the lock-up frequency band. In such cases, the loop filter allows those frequency fluctuations to pass unimpeded to the VCO.

The Countermeasure

For that reason the following countermeasure was used. The loop filter's frequency response was changed using adaptive control techniques. When not locked it has the response of the Time-optimal PLL; when locked the cut-off frequency moves lower according to the degree of lock.

When this is done, the cutoff frequency is only moved to the left and the Time-optimal PLL's transfer function is preserved. We named this PLL the Sampling Period Adaptive Controlled Tracking System: SpAct (s-pact).

The Meaning of Feed-forward Control

As I have mentioned previously, the greatest benefit of this system comes from feed-forward control.

Feedback control is a useful and powerful technique since, even if the connected device's (in this case the host's) frequency is not known, the system's frequency can easily be set by calculating the difference. However, the biggest weakness of feedback control is that the only way a frequency fluctuation in the connected device can be known is through the error; dealing with the problem is always relegated until later. In particular, the loop filter's transfer function causes delay, so it is easy for tracking pulses to arise, and it takes great intuition and experience to improve the jitter performance.

On the other hand, in feed-forward control, the receiver must know the sender's frequency. Of course the receiver's own control system must also be identified correctly, so the designer has to be alert. However, if the sender's frequency can be estimated one time, the frequency will be stable even without the feedback loop that causes delay.

In other words, SpAct deals with this using a two-stage structure: (1) The Time-optimal PLL concept is used and the sender's frequency is estimated. (2) After estimating the frequency, stabilization is accomplished using feed-forward control techniques, and crystal oscillator-like performance is preserved.

The signal wrclk is the FIFO write signal that accompanies the arrival of a USB packet. SpAct uses a frequency divider to transform this into a 1 ms signal. The Digital Control Oscillator at the right side of the figure creates the FIFO read signal and the DAC system clock. This rdclk is divided to create a 1 ms signal. The Time-optimal PLL's input signal is created by the Phase Error Detector operating on this signal and the 1 ms signal derived from the wrclk.

The section set off by a dashed line near the center of the figure is the "Extended Time-optimal PLL Circuit." The Sender Frequency Estimator and the Phase Regulator are found here. Beneath that are the State Observer and the Adaptive Controller. The Adaptive Controller uses the Phase Error Detector and the State Observer to adjust the Time-optimal PLL's feedback gain and time constant.

Figure 13. SpAct Block Diagram

SpAct's Principle of Operation

Figure 14 is an overview of SpAct's operation.

The horizontal axis is the USB packet arrival times (the reference clock) and is in discrete time. The vertical axis shows phase error. Let's follow along the horizontal (time) axis.

At first, SpAct uses all of the reference clock cycles for control. In this mode, SpAct is a Time-optimal PLL. In the beginning, the sender's frequency has not been identified, so the error is quite large; the USB specification allows for 500 ppm. Then, when the second packet arrives, the first error is measured.

Audio data begins to playback as soon as the first packet arrives. As mentioned before, since SpAct is a Time-optimal PLL, when the next packet arrives SpAct locks completely, including phase. Since Figure 14 is conceptual, the error scaling is overemphasized. But, other than the hump at the beginning, the error is extremely small.

However, even with a Time-optimal PLL, there is no getting around the frequency estimation error. There is measurement error, and system identification error. It follows that if we only had a Time-optimal PLL, it would be oversensitive to this error and begin pulsating (the loop filter has a gain high enough to lock in minimum time, after all). To resolve this, SpAct expands the sampling time.

In Figure 14, every other reference clock cycle is being skipped. The interval is chosen using "adaptive control techniques."

Figure 14. Conceptual Operation of SpAct

The Time-optimal PLL is a sample value type control system, and the change in sampling time changes the system response. But SpAct uses this characteristic in a positive sense, and preserves the Time-optimal PLL's characteristics, except that the sampling time is lengthened. An increase in the sampling time shifts the loop filter toward lower frequencies, which improves the jitter performance.

In this way, since it is able to change the sampling time according to the state of the sender frequency estimate, SpAct is a no-feedback control system. In this case, the gain of the loop filter has become zero. This can correctly be called a feed-forward control system.

Improving the Transfer Function - Scaling the Input Signal

It is necessary to use a scheme to preserve the Time-optimal PLL's performance even though the sample time changes. For that, we modify the transfer function (2 -- z^-1)/(1 -- z^-1). To make a long story short, since the object of control operates in continuous time within some boundaries, changing the sampling time within the sample value system changes the system response.

Figure 15. Changing the Sampling Time

Figure 15 is an example of what happens when changing from one sampling time to another. When the sample time is changed without also changing each sample's excursion (or time constant), the sample value system makes an error as shown by the dotted line in the figure. Here the Time-optimal PLL would mistakenly think a large error had been made. In order to correct for that, we place a scalar on the Time-optimal PLL's input. It can be thought of as a gain correction that allows the error that occurs during n clock cycles to be cancelled within n clock cycles.

The block diagram of the Time-optimal PLL, including the scale factor 1/n, is shown in Figure 16. Notice that we have changed the order of the summers for the delay elements and that the multiply by two now couples in at the end. Also, the two delay elements have been combined into one, which is in the main signal path. Physically, the multiply by 2 performs phase regulation, and on the next sample the delay element does frequency correction. For this reason, we call the left part of Figure 16 the 'Frequency Estimator' and the right part the 'Phase Regulator'.

Figure 16. The Correction to Figure 12

Considering the fact that this is a sample value system and that its operation will not be affected by anything that happens between samples, the digital implementation of this circuit can actually be realized using only a couple of counters (adders). The portion within the left dotted box is an integrator and can be realized by counting, with the clock, up or down based upon the error (the phase error output time). The counter within the dotted box on the right is taking the difference between the data of one sample time ago and twice the error. This can be realized using a loadable counter where the data from one sample time prior is reloaded into the counter every sample time, and the counter counts up or down according to twice the error. In addition, by making the sampling time lengthening factor, n, a power of two, the multiplier gate count can be greatly reduced (only a shift is needed). In this way, the heart of SpAct can be realized using only two counters (adders) and a shifter.

The Structure of the USB-DAC that uses SpAct

The block diagram for the USB-DAC that uses SpAct is shown in Figure 17. SpAct is depicted beneath and to the left of the figure's center.

The clock that is reconstructed by SpAct goes into the Audio Clock Generator which generates the system clock used in the DACs shown at the top of the diagram. In addition, the FIFO read timing is in perfect synchronization with the DAC system clock. The reference clock input into SpAct is the FIFO write clock from the USB interface. The read clock (rdclk) tracks the frequency of that reference.

Figure 17. The Block Diagram of the USB-DAC that Incorporates SpAct

Optimization of the Feed-forward Period

Since SpAct is fundamentally a Time-optimal PLL, it locks by the time of playback of the second packet and from there the feed-forward period is modified according to the state of the sender frequency estimator. Of course, during this time the phase error is continually measured, and if something unusual occurs, the operation returns quickly to that of the Time-optimal PLL.

When the adaptive condition is favorable, the feedback loop gain is zeroed for some periods. These are called "Feed-forward Control Periods." The minute fluctuations of the sender frequency are completely unobserved during these periods. In addition, during the Feed-forward Control Periods, the phase error is detected and shifted to the right by a factor of n. As a direct benefit, the number of effective bits of accuracy of the measurement increases and, with it, the accuracy of the frequency estimate increases as well. Then, the error measurement if fed back, through the Time-optimal PLL, which makes the Feed-forward Period 1, to the integrator and the error is updated in minimum time.

Proceed to Part 3...