Data converters (ADCs/DACs) are a hotbed of electronic system innovation. System designers can now implement architectural approaches that were in the very recent past limited to research papers or simply not feasible economically. Perhaps one of the most significant design challenges associated with systems employing high performance data converters is the implementation of the clock generation block used to sample the input signal. Often a design will become 'clock limited', causing the designer to rely on very expensive clock generators to bring the system within acceptable levels of performance.

This article proposal presents the topic in two parts. Part 1 provides a basic toolbox of information for designers tasked with implementing a system involving high performance data conversion. Part 1 places special emphasis on the impact that clock characteristics have on data converter performance. First, it discusses some fundamental concepts connected with clock performance. Next, it examines the 'anatomy' of a timing device. Finally, Part 1 addresses methods to tailor timing device performance specifically to the application. Part 2 will use the foundation provided by Part 1 to discuss the key trade-offs that a designer must manage at the system level.

Precision clocks and communications
The opportunity for consumers to experience our multimedia world has never been better, thanks in part to high performance analog technology. Multi-media content is assembled into packets and is routed into streams of data conveyed via the communications infrastructure. These streams require significant bandwidth, particularly when aggregated, for delivery to high definition televisions, personal video players, and mobile phones. At the macro level, this infrastructure (spanning edge/access networks and the core and transport backbone) requires a sophisticated network of precision clocks so that packets are delivered reliably and on demand.

Along this journey, content crosses the analog/digital divide via high performance data converters. It is transported via the aforementioned infrastructure to the consumer where it is converted back into a pristine high definition signal via another data converter. Precision clocks play a major role in determining system performance, whether it is via a wired or wireless transmission medium. However, the use of precision clocks is not limited to the delivery of the multimedia experience. Low noise, high precision clocks can be found in virtually any application in which large amounts of data must be communicated.

Sampling a signal: a time-domain perspective
If a perfect data converter and with a noise free clock are used to quantize Vin, Figure 1a shows a representation of the input waveform, where Figure 1b shows the input waveform (V_in) in the form of an asymmetric trapezoidal pulse.. The black dots on Figure 1b show the desired sampling points. The upper plot in Figure 1a shows the transposition of these dots. These points form a distortion free version of the original waveform.

Figure 1: Distortion and clock jitter
(top to bottom: 1a, 1b, 1c)
(Click on image to enlarge)

Also shown in Figure 1b are shaded regions which represent a range of possible times at which the sample clock edge can occur, assuming that the sample clock has a noise (jitter) component. Errant sample locations are shown as red dots. These points are within the range of possible clock edges but not in the center of the shaded area. Figure 1c shows the errant sample locations. Each value recorded on the Y-axis is the magnitude of V_in at the (errant) sampling point. Each corresponding value on the X-axis it the 'perfect' sampling point in time since the data acquisition system has no knowledge of clock noise or any way to compensate for it.

Errant samples are taken, caused solely by jitter on the sample clock. The red trace in Figure 1(c) shows the results, which is a distorted version of the original input waveform. Three key observations can be made with respect to these plots:

1. Even if the ADC is perfect, a noisy sample clock will add noise and undesired distortion. The process of sampling a signal with an ADC is much like the process of mixing in the RF world. Mixing the signal with a noisy clock has the net effect of 'spreading' the desired signals in the frequency domain as well as converting it (see Figure 2).


2. The frequency of the input signal V_in determines the degree of sensitivity to clock noise. Obviously, sampling the signal at any location if it is not changing over time does not matter (top of the trapezoid). However, the greater the input frequency is the greater the error generated by a perfect data converter if the sample clock is noisy.


3. In essence, ADCs have resolution in two dimensions: the degree of granularity of quantization (determined by the characteristics of the ADC), and, the ability of the data conversion system to consistently sample the signal at precise intervals (determined by the characteristics of the sample clock generation system and to a limited extent intrinsic ADC characteristics).

Figure 2: Sampling and Mixing
(Click on image to enlarge)

Clock performance and data-converter parameters
The level of importance that the sample clock has on ADC/DAC performance is intuitive; however, it would be helpful to understand how these observations relate to data converter performance parameters. Figure 3 shows a small segment of an input waveform. The desired sample point is shown as the point at which the ADC input switches from track to hold. The range of instances at which the actual sampling point could take place is bound by the region labeled as tj. The range of input signal levels that can be observed over the possible sampling interval is labeled ΔV_RMS.

Figure 3: Data Converter Sampling Process.
(Click on image to enlarge)

Assuming a sinusoidal input for V_in we have,

[Note: you can click on this equation or any of the ones below to enlarge.]

Differentiating with respect to time yields the signal slope,

Taking the RMS value,

Therefore, the RMS error voltage due to jitter is

Signal to noise ratio (SNR) is defined by:

Therefore, the SNR component due to jitter is:

The jitter value t_j (total jitter) in Equation 6 comprises two primary components: the intrinsic jitter of the ADC itself and the jitter of the sample clock. These parameters are stochastic and independent in nature therefore the total jitter tj is calculated by taking the root sum squared of the intrinsic ADC jitter and the jitter of the sample clock. Equation 6 can be plotted for various fixed values of jitter, Figure 4. Clocks capable of delivering jitter performance well under 1 ps RMS (1 kHz " 30 MHz) are very difficult to implement, but are nonetheless available.

Figure 4: Data Converter SNR
(Click on image to enlarge)

SNR and System Performance
Part 2 will discuss many aspects of system performance in detail. Shannon's equation is one explanation as to why SNR is such an important parameter for system performance optimization:

where C is the channel capacity in bits per second (bps) and B is the total system bandwidth in Hz.

Multimedia content requires significant channel capacity C. The designer has control over system bandwidth either through the selection of the transmission medium or by opening up receiver bandwidth. Although sometimes unavoidable, opening up receiver bandwidth can be deleterious to SNR. The bandwidth of the transmission media may not be a variable within the designer's control. This is particularly true of wireless systems in which regulatory bodies establish channel bandwidths based on the allocation of spectrum. Clearly, in this case, the designer focuses on optimizing SNR.

Jitter and phase noise
Once the impact of jitter on ADC performance is understood, the focus should now be on studying jitter. While engineers in the fields of data communications or high performance data conversion tend to specify clock requirements in terms of jitter, those who work in the field of precision timing and clocks specify clock performance using phase noise parameters. It is helpful to understand the nature of the components that comprise jitter before evaluating how phase noise and jitter are related.

Referring to Figure 5, jitter comprises two primary components: bounded (or deterministic) jitter and unbounded (or random) jitter.

Figure 5: Jitter Family Tree.
(Click on image to enlarge)

Deterministic jitter exhibits behavior that is predictable and repeatable, therefore, it can be quantified accurately with a relatively low number of observations. For this reason, deterministic jitter can be expressed as a peak-to-peak value. On the other hand, random jitter is the aggregate result of stochastic processes, which makes it less straightforward to measure or quantify. Random jitter is expressed as an RMS value, with a measurement bandwidth normally appended as a qualifier.

Phase noise is a direct measurement of the noise sources that make up the random noise component of total jitter. It is measured using a spectrum analyzer that can evaluate the power levels at various offsets from the carrier (fundamental) frequency within a 1 Hz bandwidth. For this reason, the phase noise performance is specified at discrete values with corresponding frequency offsets and is expressed in dBc/Hz, or preferably as a single sideband plot.

Most modern spectrum analyzers will calculate RMS jitter. However, having a basic understanding of how the measurement is made provides some insight into the impact that phase noise has on system performance. If the spectrum analyzer is set to measure phase noise, a single sideband plot will be displayed.

The first step to convert phase noise to RMS jitter is to integrate the power represented by the area under the phase noise plot between two specific frequency offset values (this is where the measurement bandwidth which accompanies a jitter value that is expressed in units of time_RMS originates, Figure 6). The value calculated is called the RMS Phase Error. Since the spectrum analyzer will display a single side band plot, the area read must be doubled.

Figure 6: RMS Phase Error Measurement.
(Click on image to enlarge)

Once the RMS Phase Error has been determined, the rest of the conversion process is straightforward. The function L(f) usually defines single sideband phase noise. If we define RMS Phase Error as σ_rms, then:

Therefore,

When specifying RMS jitter in a meaningful way, the values of f₁ and f₂ must be listed along with the RMS jitter value.

Anatomy of a timing device
Figure 7 presents the major functional blocks of a timing device. Timing devices can generate multiple, integer-related copies of a clean reference clock input. If the reference clock is distributed to multiple cards such that it contains additive noise due to its journey over a cable or a backplane, then a timing device can be configured to remove the phase noise (and hence the jitter) from a dirty reference clock input and then generate multiple integer-related copies of the 'cleaned' clock input. A timing device comprises a phase locked loop, a loop filter, a voltage controlled oscillator, a distribution section, skew controls, and output buffers.

Figure 7: Timing Device Functional Blocks
(Click on image to enlarge)

Timing device optimization
Finding the optimal configuration for a timing device can be an iterative exercise. The designer should be armed with a basic understanding of the impact that each block has on overall system performance. Analog companies that offer high performance timing solutions sometimes provide tools to help the designer navigate through this tricky task. National Semiconductor furnishes designers with a suite of online tools through its WEBENCH® portal specifically tailored for the signal-path designer (particularly EasyPLL for clock optimization).

The bad news is that no one configuration is correct for all applications. The good news is that there are tools available that make timing device optimization somewhat straightforward. The basic levers which a designer has at his or her disposal to shape device performance include PLL parameters, loop filter parameters, the distribution section, and skew control. In addition, the overall noise floor of the device has a significant impact on performance as well. While this article provides a cursory overview of device optimization, it is recommended that designers visit WEBENCH' as well as procure a copy of a book such as PLL Performance, Simulation, and Design Fourth Edition by Dean Banerjee (ISBN 0-9708207-1-2).

The designer can adjust certain parameters to optimize performance. Consider Figure 8 and Figure 9 below, which depict the phase noise of a timing device with the loop filter adjusted from a relatively wide loop bandwidth as in Figure 8 to a narrow loop bandwidth as shown in Figure 9.

Figure 8: Timing-device phase noise with wide loop bandwidth
(Click on image to enlarge)

Figure 9: Timing-device phase noise with narrow loop bandwidth
(Click on image to enlarge)

The reference input (shown as the TCXO trace in the plot) typically has a very steep roll-off in phase noise close to its fundamental frequency if the signal has not been permitted to pick up broad band noise sources. If it has picked up noise, then perhaps the noise doesn't roll off much at all. The primary noise contributors to the frequency output of the timing device include:

1. The reference input
2. The Phase Locked Loop (PLL)
3. The Voltage Controlled Oscillator (VCO)
4. The Distribution Section
5. The noise floor of the device

The PLL, the VCO, and the noise floor of the device all 'job share'; and their primary job descriptions include frequency translation and noise reduction. Setting the loop filter cut off frequency determines when the VCO takes over for the PLL in performing noise attenuation. To a large extent, the phase noise level at very large offsets is determined by the device noise floor and to some extent the VCO. The VCO tends to dominate total noise performance in a configuration using a narrow loop bandwidth as shown in Figure 9. If the PLL has excellent performance close to the carrier, then the loop filter should be adjusted away from the carrier so that it can filter any noise from the reference input. This is a good configuration, particularly if the VCO has excellent phase noise performance at far (perhaps >50 kHz) offsets.

Conclusion
Determining the ideal configuration for a timing device used to clock high performance data converters is an iterative exercise. The designer's journey through this jungle of optimization is survivable, if he or she is armed with a good understanding of the underlying issues involving ADC signal to noise performance and is provided with a good set of tools that enable experimentation. While spending time optimizing a portion of the design that is perceived as an adjunct to the data converter itself may seem on the surface to be mundane, the consumer will see and hear the 'high definition' difference.

(You can read Part 2 by clicking here)

Author Biographies
John Johnson is the Director of Applications Engineering and the Business Unit Manager for the Precision Timing Group which is part of the Interface Division of National Semiconductor. John has 25 years of experience in the electronics industry and has worked in the fields of product development, marketing, applications engineering, and business management.

Jim Catt is a Principal Applications Engineer for the Precision Timing Group of the Interface Division of National Semiconductor. He has 20 years of experience, primarily as a project manager, systems engineer and design/development engineer in the communication test equipment and defense industries.