Challenges of clocking a high-definition world, (Part 2 of 2): A system applications perspective

Abstract
Part 1 of this two-part series (click here) covered the fundamental aspects of jitter relative to clocking an ADC and the impact of jitter on the sampled signal. It derived the fundamental expression for SNR due to jitter. Then the article discussed the different types of jitter and their sources, as well as the relationship of sample-clock phase noise to jitter. In conclusion, it diagramed the functional blocks of a timing device along with the adjustable parameters to achieve the performance required for a specific application.

In part II of this series, we adopt a system level focus. We begin by examining issues specific to communication systems that are evolving from multi-module, single channel architectures to single-module architectures. Single-module architectures shift the multi-channel processing to the digital domain by sampling wide-band, multi-channel signals at high intermediate frequencies. These architectures often use sub-Nyquist sampling. We discuss the implications of this evolution for ADC performance and review the influence of sampling clock phase noise under the assumption of sub-Nyquist sampling. Finally, we show how to analyze the impact of multiple, uncorrelated noise sources on overall SNR, relate this to clock jitter, and present an example that illustrates the different jitter requirements for different ADC resolutions.

One important trend in the multimedia world is the expansion of the digital frontier in order to take advantage of the economics of Moore's law and other inherent advantages of the digital world. Because analog circuitry does not obey Moore's Law, the analog world has not seen the dramatic improvements in size and power that have occurred in the digital world. Hence, communication system designers are employing higher intermediate frequencies and higher bandwidths, placing greater demands on data converters and associated clocking devices, converting signals from the analog domain to the digital domain at higher and higher frequencies in order to reap the benefits of Moore's law.

A small number of companies, such as National Semiconductor, have responded by designing higher speed data converters with higher bandwidths, along with the timing devices that these converters need to achieve optimal performance. For example, National's 8-bit ADC08D1500 achieves excellent performance (> 7 ENOB) at sampling rates of 1.5 gigasamples per second (3 GSPS in dual-edge sampling mode), with an input bandwidth of 1.7 GHz. Its LMX2531 VCO/PLL family can deliver sampling clock performance well below 1 picosecond RMS jitter. These devices have enabled system designers to sample wideband, multi-channel signals at IF frequencies in the hundreds of megahertz.

In addition to the performance gains in data converter devices, the use of bandpass sampling, or sub-Nyquist sampling, is another critical aspect of these systems. While this technique enables more practical sampling rates, it also brings an additional dimension to noise analysis and its impact on data converter requirements. In the remainder of this article we will look at some of the system level issues that must be considered in determining timing device requirements, specifically jitter.

Another observable trend is higher functional integration. In the communications domain, multi-module architectures as shown in Figure 10 are being replaced by architectures with a single device at their core, Figure 11. Despite the obvious technical challenges that come with this architecture, the benefits are attractive: simplicity, flexibility, and performance.

Figure 10: Multi-module architecture
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Figure 11: Single, high-performance ADC implementation
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System-level design drivers
The designer must be cognizant of the system-level influences on design choices and how these impact the performance of his or her part of the system. Figure 12 is a hypothetical example showing devices upstream from the target system. The designer must understand their performance, but cannot necessarily control or even influence it. Specifically, upstream devices and systems introduce noise and alter channel characteristics (gain, frequency response, etc.) that must be accommodated at the interface to the ADC.

Figure 12: End-to-end signal path
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Figure 12 shows the channelization of multi-channel signals in the digital domain. Sampling multi-channel signals increases the dynamic range requirements at the ADC interface due to both the increased power from the desired signals and the increased noise power due to higher bandwidth looking into the ADC. Multi-channel signals will also have a higher peak-to-average power ratio (PAR) which means that more of the ADC dynamic range is consumed by overhead margin than is typically allocated when sampling a single channel signal.

Together, these phenomena can increase the required ADC resolution. Sub-Nyquist sampling can adversely impact SNR due to noise aliasing in the sampling process if noise at the ADC input is not controlled or accounted for.

Ultimately, SNR is the key performance metric. In sampled data systems, the designer must contend with noise sources such as thermal noise, local oscillator (LO) phase noise, crosstalk and spurs at the ADC interface. Internal to the ADC, there are noise contributors such as substrate noise, power supply noise, 1/f noise, quantization noise, phase noise on the sample clock, quantizer non-linearities (DNL, INL), and in interleaved architectures, channel mismatches. The designer must understand and account for each of these potential sources in choosing ADC resolution, sampling rate, and signal processing algorithms.

To the extent that he or she is also designing the signal path upstream from the ADC, the impact of design choices for the upstream path must also be factored into performance of the sampled data part of the system. Understanding the effect of upstream influences is important because they constrain the noise budget available to the designer. Quantifying the noise budget allows the designer to specify the performance required of the sample clock or data clock used in the system.

Part I of this series discussed how the sample clock phase noise (or jitter) has a direct impact on SNR (Figure 13). The time domain multiplication is convolution in the frequency domain. The perfect sinusoid at the input (impulse in the frequency domain) after mixing with another noisy sinusoid becomes a noisy sinusoid at the output. This is analogous to the sampling operation in an ADC.

Figure 13: Sampling and mixing
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To understand the impact of phase noise on the sample clock, let us review the mathematics of the sampling operation. The multiplication of the input signal, x(t), by a train of perfect impulses represents the idea sampling operation (Figure 13). This process yields a stream of sample values, y(nT), Equation 1

[Note: you can click on this equation or any of the ones below to enlarge.]

Mathematically, multiplication in the time domain is the dual of convolution in the frequency domain. However, a train of ideal impulses in the time domain transform to a train of impulses in the frequency domain. Convolving this with the signal spectrum simply results in the familiar periodic signal spectrum of digital signals.

In reality, the sampling waveform is neither a perfect impulse nor is it stable in time. Instead, it is more realistic to consider the final sample voltage as a weighted average of the input signal over some very small time window. However, because we are primarily concerned with the impact of clock jitter, we'll continue to use the impulse as the sampling waveform, but with a jitter term included. If the effect of clock jitter is included, then the delay term in the impulse function includes a random component, τ_j. Typically, τ _j is modeled as a Gaussian random process with zero mean and standard deviation σ_j. The sampled signal is now:

Equation 2 shows us that the input signal is spread by the jittered sampling function. In essence, the exponential term results in small, residual spectrum shifts (modulation) that spread the signal band. Figure 14 illustrates this effect.

Figure 14: Bandpass sampling
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Two steps illustrate the effect embodied in Equation 2. The jitter term modulates the original signal spectrum shown in Figure 14a (with sample clock). Figure 14c shows the digital, jitter-modulated spectrum after sub-Nyquist sampling. Jitter has an impact on the signal band in two ways. First, residual spreading caused by the jitter (due to the close-in phase noise, Figure 14b) directly degrades in-band SNR. Second, sub-Nyquist sampling causes out-of-band noise to be aliased into the signal band, further increasing the noise floor. In Figure 14c, the out-of-band noise that "crosses" the frequency boundaries that are multiples of π (marked by the vertical dotted lines) will fold back into the signal band.

If this out-of-band noise is high enough, it will significantly raise the noise floor. These combined effects emphasize the importance of both close-in phase noise and phase noise at large offsets from the clock frequency. This effect can be somewhat mitigated by increasing the sampling rate, which would cause the images to be more widely separated in frequency, but the tradeoff is that the number of samples to be processed is increased. However, this may be an acceptable tradeoff in some applications. This example also reinforces the importance of filtering in the signal path to limit the out-of-channel noise at the ADC input.

In the next section, we examine how the effects of several noise contributors can be combined into an expression for clock jitter, allowing one to study the impact of the different sources and to place an upper bound on clock jitter. In this example, we will combine thermal noise, quantization noise and sampling clock phase noise. If we assume that each of these noise sources is independent and uncorrelated (a reasonable assumption), then we can express a composite SNR as follows:

Though we often think of SNR in the log domain, note that the terms in the above expression are linear. We have used variance notation in the first form of the expression to emphasize that we are working with random processes, which can even include the desired signal.

To find the SNRs for each noise source, we will start with thermal noise. The power in the thermal noise appearing inside some fixed bandwidth Δf is the noise density multiplied by Δf:

P_th-noise = N₀ * Δf = σ²_T, where N₀ = the noise spectral density in units of W/Hz.

Establishing a value for N₀ at the ADC input requires the designer to perform an end-to-end analysis of the signal path to find a system noise figure. Referring back to Figure 12, each of the subsystems (receivers, signal distribution amplifiers, splitters, and cables) has an associated gain and noise figure. These are combined to obtain a final system noise figure, Equation 4 (see Reference 1 for a more complete discussion of noise figure).

where the subscripts indicate successive subsystems (or components) in the path, and the parameters F_n and G_n are the linear values of noise figure and gain for each subsystem or component included in the analysis.

If there are several components in the signal path, this may appear to be a daunting exercise. However, there is salvation to be found in that the final system noise figure is dominated by the first component in the path. Note that as successive subsystems or components are included in the calculation, their contribution to noise figure is inversely proportional to the product of the gains of upstream subsystems, i.e., each downstream subsystem or component has a quickly diminishing affect on the overall noise figure. Experienced system designers know this and hence, the first component in the path is usually a low noise amplifier that essentially sets the system noise figure at a low value.

So, if the signal path upstream from the ADC is extensive, a reasonably good estimate of the system noise figure can be gotten by only looking at the first few subsystems (components) in the path. Once a value for NF_sys has been estimated, it is used to find the power spectral density of the noise at the ADC input using Equation 5 (in dBm/Hz):

This power spectral density is important for two reasons. First, ADCs with a wide input bandwidth can incur a dynamic range penalty because the noise power (σ²_T) is proportional to the bandwidth. Second, though baseband processing usually includes a filtering step that will eliminate all noise that does not fall within the band of interest, the remaining in-band noise contributes to the overall SNR calculation. In the log domain, the noise power is the log of the spectral density plus 10log of the bandwidth being considered:

To find the noise power in the band of interest (in dBm), we substitute the signal bandwidth for Δf_BW:

If the signal power in dBm is known, we can subtract the noise power to get an SNR value in dB, and then convert this to a linear value. Alternatively, we can convert the noise power to an equivalent RMS voltage and write the SNR in terms of RMS voltages:

The second noise source to be accounted for in this example is quantization noise. The limited resolution of the ADC introduces quantization noise, Figure 15. The typical transfer function for an offset binary quantizer is shown. The horizontal axis, representing the input voltage range of the quantizer, is divided into fixed intervals of width 1 LSB. Each sample value of the input voltage is mapped to one of these intervals.

Figure 15: Quantizer model
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In essence the quantizer rounds down the sampled voltage value to the value represented by the quantized interval. In Figure 6, any value of V_in = V(nT_s) that falls in the interval of 7Δ/2 to 9Δ/2 is mapped to the digital value 0100. If we convert this digital value back to a voltage, we would assign a value of 7Δ/2 = (7/2)*(V_ref/2^N).

In fact, the true voltage value was larger, so the quantizer has introduced an error voltage, V_e. This error term (quantization noise) can be viewed as additive to the true signal value. Because the distribution of any ensemble of input voltage values that fall within a particular quantization interval is uniform, the distribution of the error term, or quantization noise, is also uniform. The quantization noise power is the variance of this error term, which is:

To find the quantization noise power referred to the ADC input, we divide by the input resistance R. Finally, we calculate the quantization noise power spectral density by dividing by F_s/2:

After converting this to log domain equivalent in dBm, we can calculate the in-band quantization noise power as we did for thermal noise, and then compute the SNR using either power values or RMS voltage values. Note that the quantization noise power spectral density is inversely related to ADC resolution (N) and sample rate (F_S). Consequently, if we express SNR in RMS voltage terms, we can study the impact of different resolutions and sample rates on SNR.

If there were no jitter on the sample clock, then the noise power spectral density in the signal band (in-band) will be set by the sum of thermal noise and quantization noise (in this example). In this case the baseline SNR is:

In Equation 12, the designer can use the terms for each of these SNRs to incorporate the effect of different parameters such as sampling rate and ADC resolution. The impact of these parameters can be studied in order to set bounds on them to meet a target SNR (or ENOB). Having done this and selected tentative values for N and F_S, the degradation of SNR due to sample clock jitter can be introduced. Part 1 of this article showed that the SNR due to sample clock jitter is:

It is important to remember that in this equation σ_j is actually the root-sum-square value of the RMS jitter of the clock plus the RMS aperture jitter of the ADC. Using Equation 13 for SNR due to jitter, and combining it with Equations 3 and 12, we can construct an expression for jitter that incorporates the baseline SNR and an SNR degradation budget parameter:

In Equation 14, x is the specified acceptable degradation in total SNR due to jitter (in dB), f_sig is the highest frequency in the signal of interest, and the other parameters are as described above. The inequality allows us to set an upper bound on jitter. Alternatively, we can simply specify a target (minimum acceptable) SNR based on our application and use a modified form of Equation 14:

As an example, consider a WCDMA system that samples a signal centered at 245 MHz, with a bandwidth of 5 MHz, at a rate of 61.44 MSPS. An automatic gain control (AGC) circuit in front of the ADC is configured to maintain the average signal power at the ADC input at -10 dB full scale (dBFS). The ADC input range is 1 V_p-p, and the thermal noise power at the ADC input is fixed at -90 dBm in a 5 MHz bandwidth.

Figure 16 shows the plots for three different ADC resolutions: 8, 10, and 12 bits. In all three cases, quantization noise is setting the noise floor. For each case, the traces show the degradation in SNR as jitter increases. For the 12-bit ADC, the maximum jitter limit remains well less than 1 picosecond, even as the SNR degrades from 72 dB to about 59 dB.

Figure 16: Jitter versus SNR
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Conclusions This article has discussed some of the more challenging aspects of system design when implementing a high performance multi-channel, digital receiver architecture when using bandpass sampling. For the ADC, this implies very high input bandwidths as well as high sample rates. Our emphasis in this article has been on design from a system perspective, meaning that design choices, such as ADC speed and resolution, along with sampling clock requirements, can be driven by system characteristics upstream from the ADC interface.

The selection of an appropriate low noise amplifier (LNA) on the system front end has the most significant impact on overall noise figure, which in turn sets the noise density at the ADC input. Furthermore, the generation and distribution of a low noise sample clock can dominate system performance. The impact of sampling noise due to jitter on overall SNR must be assessed in the context of all other noise sources, such as thermal noise and quantization noise, to determine the sample clock performance necessary to achieve the desired in-band SNR.

References
1. T. T. Ha, Digital Satellite Communications, 2nd Edition, McGraw-Hill, New York, 1990.
2. M. E. Waltari, K. A. I. Halonen, Circuit Techniques for Low-Voltage and High-Speed A/D Converters, Kluwer Academic Publishers, Boston, 2002.

About the authors
John Johnson is the Director of Applications Engineering and the Business Unit Manager for the Precision Timing Group which is part of the Interface Division of National Semiconductor. John has 25 years of experience in the electronics industry and has worked in the fields of product development, marketing, applications engineering, and business management.

Jim Catt is a Principal Applications Engineer for the Precision Timing Group of the Interface Division of National Semiconductor. He has 20 years of experience, primarily as a project manager, systems engineer and design/development engineer in the communication test equipment and defense industries.