Engineer's guide to HDMI ESD protection: Part 1

Early 'throwaway' choices in the design cycle, such as discrete component or PCB stackup definition, can often be more critical than esoteric scaler and link layer design or HDMI ASIC selection issues. Many common misunderstandings about ESD (electrostatic discharge) protection components can be easily avoided in your next HDMI design (see Page 3 for a list of perfromance metrics and ESD 'gotchas.')

This is the first of a two part series that examines system ESD protection design issues. Part 1 looks at the protection options and specifications. Part 2 will look at the resultant signal integrity issues involved in ESD protection selection.

While achieving higher resolutions and pixel depths in HDMI 1.3, integrated circuit manufacturers have continued to decrease the minimum dimensions of the transistors, interconnections, and the SiO₂ insulation layers in their devices. This results in smaller structures for higher speed devices which are more susceptible to breakdown damage at lower energy levels. SiO₂ layers are more likely to rupture and metal traces are more likely to open or bridge during an ESD event.

HDMI receivers and transmitters will include some on-chip ESD protection for a controlled manufacturing environment, but a typical real-world ESD zap can deliver a peak current of over 30 Amps, and enough I²R heating to permanently destroy the relatively small input clamps in the deep sub-micron HDTV receiver, or DVD transmitter IC (See Figure 1). An 8kV IEC 61000-4-2 ESD pulse is the industry standard approximation of stepping across the carpet on a cold Christmas morning to plug the new video game into the family television.

To survive this repeatable test, larger external ESD protection clamps must be used to divert this energy back to earth ground without damaging the HDMI (or other I/O) IC. These external analog clamps are generally fabricated in geometries that are dictated by power handling capacities, and do not benefit from the standard cost improvements of process scaling. In fact, these 8kV ESD protection clamps are more cost effective by being fabricated in older, larger geometry processes.

At the same time, controlled impedance microstrip TMDS interconnects on the PCB are likely to be some of the most critical signal integrity focal points in an HDTV or DVD design. As bit rates climb, the interconnect pathway's bandwidth can quickly become a bottleneck for critical harmonics which may be 4-5GHz higher than the TMDS fundamental.

So the system designer's problem blossoms into two areas: (1) Add protection to shunt destructive energy away from delicate ASICs during ESD strikes, and (2) maintain interconnect signal integrity during normal operation.

ESD protection system interaction
ESD strikes are wide-bandwidth events with very fast rise times and large peak energy pulses. Once this energy enters the HDMI cable or connector, the ESD protector and ASIC must divide the resultant current.

Figure 1: IEC 61000-4-2 Pulse Shape

When the ESD protector begins to clamp, it shunts current into (or out of) ground. At the same time, the ASIC has seen some of this rising edge and it may begin to conduct as well. This sharing of the current is the critical element of system level ESD design which cannot be specified on a single component datasheet alone.

Next: System ESD example