Design Article
Building an Embedded Asterisk PBX Part 3
David Rowe, President Rowetel
12/26/2006 11:09 AM EST
Editor's note: the Open Source Asterisk PBX software was the subject of three articles on Audio DesignLine:
Build a PBX using Asterisk
Building an Embedded Asterisk PBX Part 2
Linux PBX Part 2
Linux PBX Pt 3
Low level analog signals from the telephone line connected to the
analog handset.
A digital interface containing a 2.048MHz TDM bus and SPI interface
that connects to the fast rise time (i.e. noisy) signals from the
Blackfin.
A switch mode DC-DC converter that converts a low voltage 7-12VDC
rail to the -90VDC required for the telephone "battery" supply and
also generates the 200Vpp ring voltage.
It is important to prevent the DC-DC converter and digital side from injecting noise into the sensitive low level analog section. Based on tips from the Silicon Labs app notes a few tricks were used:
+ The DC-DC converter ground was kept isolated from the ground plane, and only connected at a single point. This prevents large ground current spikes from entering the ground plane. Large current pulses in the ground plane get converted to voltages (as the ground plane impedance is small but non-zero) which then get superimposed on the low level analog signals as unwanted noise. You can see the lack of ground plane in the upper left hand part of Figure 3.
+ A ground plane was used throughout the analog section, and in the digital section. The two ground planes are only connected at a single point to prevent digital currents flowing through the analog section and inducing noise. This point is as far away from the DC-DC converter as possible.
Now lets take a look at the daughter board. To reduce EMI the suppression components (e.g. ferrites and capacitors) for each port were placed on the daughter board, as close as possible to the RJ11 connectors. Each digital line in the daughter board also has series termination resistors. These resistors are initially loaded as 0 ohms, but this can be increased to combat EMI or ringing issues if required. A 74LV244 buffer (U2) is also used to reduce the edge rates of high speed digital signals from the Blackfin STAMP card. Reducing the edge rates reduces EMI as slow rise and falls times means reduced high frequency energy.
The SD card provides ample storage for the large Asterisk program and prompt files - the Blackfin can only directly address 4M of flash and Asterisk requires perhaps 16M with a full set of prompts.
A Xilinx CPLD (U4) is used to decode the SPI chip select signals for each module and support a "stacking" architecture where several boards can be stacked on top of each other to obtain extra analog ports.
The CPLD firmware was developed using the open source Icarus Verilog software, also part of the gEDA package of open EDA tools. Figure 4 shows an example of two cards stacked to obtain a total of 8 ports. Using this design it is also possible to add daughter cards containing ISDN line interfaces or additional DSP resources.
Build a PBX using Asterisk
Building an Embedded Asterisk PBX Part 2
Linux PBX Part 2
Linux PBX Pt 3
The PCB layout for this design is quite challenging as there are
three distinct signal areas in the small 50 x 25mm area:
It is important to prevent the DC-DC converter and digital side from injecting noise into the sensitive low level analog section. Based on tips from the Silicon Labs app notes a few tricks were used:
+ The DC-DC converter ground was kept isolated from the ground plane, and only connected at a single point. This prevents large ground current spikes from entering the ground plane. Large current pulses in the ground plane get converted to voltages (as the ground plane impedance is small but non-zero) which then get superimposed on the low level analog signals as unwanted noise. You can see the lack of ground plane in the upper left hand part of Figure 3.
+ A ground plane was used throughout the analog section, and in the digital section. The two ground planes are only connected at a single point to prevent digital currents flowing through the analog section and inducing noise. This point is as far away from the DC-DC converter as possible.
Now lets take a look at the daughter board. To reduce EMI the suppression components (e.g. ferrites and capacitors) for each port were placed on the daughter board, as close as possible to the RJ11 connectors. Each digital line in the daughter board also has series termination resistors. These resistors are initially loaded as 0 ohms, but this can be increased to combat EMI or ringing issues if required. A 74LV244 buffer (U2) is also used to reduce the edge rates of high speed digital signals from the Blackfin STAMP card. Reducing the edge rates reduces EMI as slow rise and falls times means reduced high frequency energy.
The SD card provides ample storage for the large Asterisk program and prompt files - the Blackfin can only directly address 4M of flash and Asterisk requires perhaps 16M with a full set of prompts.
A Xilinx CPLD (U4) is used to decode the SPI chip select signals for each module and support a "stacking" architecture where several boards can be stacked on top of each other to obtain extra analog ports.
The CPLD firmware was developed using the open source Icarus Verilog software, also part of the gEDA package of open EDA tools. Figure 4 shows an example of two cards stacked to obtain a total of 8 ports. Using this design it is also possible to add daughter cards containing ISDN line interfaces or additional DSP resources.
1
2
Navigate to related information
